From patchwork Wed May 28 13:47:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 31066 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f72.google.com (mail-pa0-f72.google.com [209.85.220.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B551720068 for ; Wed, 28 May 2014 13:47:24 +0000 (UTC) Received: by mail-pa0-f72.google.com with SMTP id rd3sf51151974pab.7 for ; Wed, 28 May 2014 06:47:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=Fly5tai7B1H+Jo/RI1q/B0KKyEPo3gvi9RMXVUTm39E=; b=gn6KvKy7LbjJWFTGPK1AoW4jYQOJkdV2oYofg61Ku633zjKaQ+LSwDjzfYrhRl/bil q0cLic1xPs0r5TwGMGVG2g2pY+AAoNlMZU5zoSjTWCIrxkdvv4oYBhi/3JeYysDL6Een 9U8VyNl/07QGB7hvi561l364m7tTutte2ZIoAkilR9AJNSqjdRbAlPWJOLNZccVCXhfS 1+GbXtpzoDCzAc8vAgPQJWu7an4tNoPZZMcrJBs/ia1TH4O5lfQ0Rb7aEng6upJgGHd+ QXKWzDdmByaB1ftcqjupJxocMhpIcY8QBTjW0EqlkuYrBr6AxfzLnMi9RjcGgSq3jW+S /YFQ== X-Gm-Message-State: ALoCoQmt77lNzpR0axoQcZ6YjsxocKuGvfHOUqgBbUZw212aKoT4Ye8iAJhMZEQ6P0h6AWNVu/im X-Received: by 10.66.169.231 with SMTP id ah7mr17609470pac.40.1401284843788; Wed, 28 May 2014 06:47:23 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.102.87 with SMTP id v81ls109631qge.0.gmail; Wed, 28 May 2014 06:47:23 -0700 (PDT) X-Received: by 10.220.160.67 with SMTP id m3mr1288681vcx.56.1401284843477; Wed, 28 May 2014 06:47:23 -0700 (PDT) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id im2si10575028veb.47.2014.05.28.06.47.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 May 2014 06:47:23 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id oz11so12497683veb.17 for ; Wed, 28 May 2014 06:47:23 -0700 (PDT) X-Received: by 10.220.53.72 with SMTP id l8mr34505590vcg.16.1401284843398; Wed, 28 May 2014 06:47:23 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp204370vcb; Wed, 28 May 2014 06:47:22 -0700 (PDT) X-Received: by 10.66.233.101 with SMTP id tv5mr43736060pac.92.1401284842315; Wed, 28 May 2014 06:47:22 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ls17si23820518pab.194.2014.05.28.06.47.21 for ; Wed, 28 May 2014 06:47:21 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754157AbaE1NrM (ORCPT + 27 others); Wed, 28 May 2014 09:47:12 -0400 Received: from mail-we0-f175.google.com ([74.125.82.175]:35001 "EHLO mail-we0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754123AbaE1NrJ (ORCPT ); Wed, 28 May 2014 09:47:09 -0400 Received: by mail-we0-f175.google.com with SMTP id p10so2476173wes.34 for ; Wed, 28 May 2014 06:47:07 -0700 (PDT) X-Received: by 10.180.105.72 with SMTP id gk8mr48646094wib.32.1401284827394; Wed, 28 May 2014 06:47:07 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-149-4-211.as13285.net. [78.149.4.211]) by mx.google.com with ESMTPSA id cz8sm43390566wjc.11.2014.05.28.06.47.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 May 2014 06:47:06 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v4 07/13] mmc: mmci: add 8bit bus support in variant data Date: Wed, 28 May 2014 14:47:02 +0100 Message-Id: <1401284822-16728-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 729105b..2f4cdf3 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @clkreg_8bit_bus_enable: enable value for 8 bit bus * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -72,6 +73,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int clkreg_8bit_bus_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -113,6 +115,7 @@ static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 16, .sdio = true, .pwrreg_powerup = MCI_PWR_ON, @@ -139,6 +142,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, @@ -154,6 +158,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -314,7 +319,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) clk |= MCI_ST_UX500_NEG_EDGE;