From patchwork Wed Sep 30 08:31:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 286604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3957C47425 for ; Wed, 30 Sep 2020 08:31:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66C432184D for ; Wed, 30 Sep 2020 08:31:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="n9UTJ+yV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728429AbgI3Ib3 (ORCPT ); Wed, 30 Sep 2020 04:31:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:47426 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725836AbgI3Ib2 (ORCPT ); Wed, 30 Sep 2020 04:31:28 -0400 X-UUID: 56abb9944fe540d3a5e9f02f5d8c22d7-20200930 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0Ehsd84DhPcJo2TiyXzbI+msjs3dkjwBe4EhIOpRVKA=; b=n9UTJ+yVH2BTaapciqu8e/9BqaCEKR3+y9sgdJ3AwgWFyvizGmzPDE9rCX+9YfTS9y8O15eaQw2wJQzudVWi68USq26RQFWmNSgCAZULNbQeA9RVDrKQaEBndHgJ+ar3YdKMrTGSrDBwGru+wbL38R9sKMs13EUtEqFlK5ECskY=; X-UUID: 56abb9944fe540d3a5e9f02f5d8c22d7-20200930 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1786876965; Wed, 30 Sep 2020 16:31:25 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Sep 2020 16:31:23 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 16:31:22 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [PATCH v3 2/4] mmc: dt-bindings: add support for MT8192 SoC Date: Wed, 30 Sep 2020 16:31:18 +0800 Message-ID: <20200930083120.11971-3-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930083120.11971-1-wenbin.mei@mediatek.com> References: <20200930083120.11971-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org MT8192 mmc host ip is compatible with MT8183. Add support for this. Signed-off-by: Wenbin Mei --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 7f89cbdc52a5..81d2951bfc37 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -29,26 +29,37 @@ properties: - items: - const: mediatek,mt7623-mmc - const: mediatek,mt2701-mmc + - items: + - const: mediatek,mt8192-mmc + - const: mediatek,mt8183-mmc clocks: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 4 + maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). - description: independent source clock gate (required for MT2712). - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + - description: msdc subsys clock gate (required for MT8192). + - description: peripheral bus clock gate (required for MT8192). + - description: AXI bus clock gate (required for MT8192). + - description: AHB bus clock gate (required for MT8192). clock-names: minItems: 2 - maxItems: 4 + maxItems: 8 items: - const: source - const: hclk - const: source_cg - const: bus_clk + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg pinctrl-names: items: