From patchwork Sat Aug 20 19:57:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7D2C32796 for ; Sat, 20 Aug 2022 19:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233284AbiHTT65 (ORCPT ); Sat, 20 Aug 2022 15:58:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232447AbiHTT6n (ORCPT ); Sat, 20 Aug 2022 15:58:43 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 248AC30F50 for ; Sat, 20 Aug 2022 12:58:43 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id z187so7017644pfb.12 for ; Sat, 20 Aug 2022 12:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=r5Va0qkg/o7OQRjyMaC+xf7CXpWYggohofnAWq4WcBw=; b=DVK6OyTZNlpmQnsQ3cXJ2p1VV1dmy4Dnl/9IkYYSzPVzH4NP+1wEpt2tnjARt66n4X 1yi3/0nmrQm1FDI8L02wL6hA5EPLqiH7QEfRKaI+TzDdq44vll1jjsdxTQc3+hjDPkYL oTy9k91EauKe5Ne5ZZd4Ye0cLU73xKwBm6u4p/H7gGebndTIyhU7cIX3iDxCvL7JMxgx 3fpgTCYfkBgzttaP7nqgpew096Vkdf2UaHWwSE8u0D8N2WmSvV4bLblwoiqSAzQwjnv+ d9P/dUqh3L9wAA+2br/Ax4dnMePNgeiLcljUJt2fG0ee8yDpqhnuA4cm+MZt23G2HWuk qPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=r5Va0qkg/o7OQRjyMaC+xf7CXpWYggohofnAWq4WcBw=; b=KMzuv7ALq7GBAw3PNoUWAt2diCu1sNR+kmJexrP2rH3vBnMeR+6Sm2x27nuQOQZt5P 92egRdZCjtoUevYJt7xNGlBBgopZUXbtetXTJfGT7Ev7ehD/ZeYNS+uhnfCerxncca2E k8Vvo++7GN+amX7+wzL5ZKpmyJycWtxxKz591E1CUjcdnoBqrDn0YhVTPkVCerDUcvrE 02U25i9oXDuyWg052yLP32JAJJ24C1rJP5tOXkRdC96DklEn6gUN7WP387rzNudRh4k5 HKWrj5ebVUCEd9hix0WPM6I9nTFuBWmCSAD2bcTDyYttIZ/j2ntFrfQQ8H+fSbufnyiC zSzQ== X-Gm-Message-State: ACgBeo0on0rr6EVd+bjjt/r6Cl9pb5EVvR4ghdnLI2w+TF42PewcSabD c2PKpsisUhXLh9UiyEEjf65a2Q== X-Google-Smtp-Source: AA6agR4kTu9QYEiMDBoNEHjThrTE0aIC/ArVls8Bao2W5ipeJdInNbM+CAx4OqnWL+S+2U17uKzssw== X-Received: by 2002:a62:4c2:0:b0:52e:bd4d:50e1 with SMTP id 185-20020a6204c2000000b0052ebd4d50e1mr14061109pfe.8.1661025522568; Sat, 20 Aug 2022 12:58:42 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:41 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 11/17] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Sat, 20 Aug 2022 12:57:44 -0700 Message-Id: <20220820195750.70861-12-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 72b1a5a2298c..fe1e96e93091 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -39,6 +39,7 @@ #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(4) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -87,6 +88,7 @@ struct cqspi_st { bool use_dma_read; u32 pd_dev_id; bool wr_completion; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -952,6 +954,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1667,6 +1676,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->use_dma_read = true; if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) cqspi->wr_completion = false; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1789,6 +1800,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pen_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1814,6 +1829,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pen_cdns_qspi, + }, { /* end of table */ } };