From patchwork Mon Nov 28 13:32:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 630540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 031FCC4167D for ; Mon, 28 Nov 2022 13:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbiK1Ndh (ORCPT ); Mon, 28 Nov 2022 08:33:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231666AbiK1Ndg (ORCPT ); Mon, 28 Nov 2022 08:33:36 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAC622DD0 for ; Mon, 28 Nov 2022 05:33:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669642415; x=1701178415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q+fihb1vyqHig+GbCUNck5ZdIIYMDhBhc7L4g7a+QTI=; b=Vo6ddbNIGECJZbSkkh3TzzLCQiAKlS/0k12sFJHTUdQbi4Yz8agPiF92 c2lmy+Q927Ur9rqf1C+Y5w1k94tXtoEUhWPSf/2Mcjy2NXKYQClSbCS0k 7YIjdiyVR/yuQG8i8c3wA0SLW0dYlJlQt8C8+W7iyJaDza9wQGv3gKdqh HGbcfYgtpAsN46f2bgFhQYD0iDtHq2SVo9SzqCGUYJd/EJmLFjicDcNyz WnkefpZuiFBdaBZrQV3dipHfPF2cS6f72T71ZCC45lnTG26nDvuO4Tz0b ujSxIzsKNvH/j8+gtNDtT+wo00MWpSdXsEChU2mRUb3Sy+uhHw9JrOQSF w==; X-IronPort-AV: E=McAfee;i="6500,9779,10545"; a="401121850" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401121850" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:33:35 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10545"; a="676044572" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="676044572" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO ahunter-VirtualBox.home\044ger.corp.intel.com) ([10.252.50.218]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:33:29 -0800 From: Adrian Hunter To: Ulf Hansson Cc: Sarthak Garg , Florian Fainelli , Al Cooper , Haibo Chen , Andrew Jeffery , Eugen Hristev , Vignesh Raghavendra , Prabu Thangamuthu , Manjunath M B , Ben Dooks , Jaehoon Chung , Viresh Kumar , Thierry Reding , Hu Ziji , Wolfram Sang , Sascha Hauer , Brian Norris , Wenchao Chen , Chevron Li , linux-mmc@vger.kernel.org Subject: [PATCH V2 3/4] mmc: sdhci: Avoid unnecessary ->set_clock() Date: Mon, 28 Nov 2022 15:32:58 +0200 Message-Id: <20221128133259.38305-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128133259.38305-1-adrian.hunter@intel.com> References: <20221128133259.38305-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org To avoid glitches on the clock line, the card clock is disabled when making timing changes. Do not do that separately for HISPD and UHS settings. Tested-by: Haibo Chen Signed-off-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 37 ++++++++++++++----------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17e5ccf9a855..beb1fe643634 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2400,8 +2400,21 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (host->version >= SDHCI_SPEC_300) { u16 clk, ctrl_2; + /* + * According to SDHCI Spec v3.00, if the Preset Value + * Enable in the Host Control 2 register is set, we + * need to reset SD Clock Enable before changing High + * Speed Enable to avoid generating clock glitches. + */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_CARD_EN) { + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + if (!host->preset_enabled) { - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); /* * We only need to set Driver Strength if the * preset value enable is not set. @@ -2424,30 +2437,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); host->drv_type = ios->drv_type; - } else { - /* - * According to SDHC Spec v3.00, if the Preset Value - * Enable in the Host Control 2 register is set, we - * need to reset SD Clock Enable before changing High - * Speed Enable to avoid generating clock gliches. - */ - - /* Reset SD Clock Enable */ - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - clk &= ~SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - - /* Re-enable SD Clock */ - host->ops->set_clock(host, host->clock); } - /* Reset SD Clock Enable */ - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - clk &= ~SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - host->ops->set_uhs_signaling(host, ios->timing); host->timing = ios->timing;