From patchwork Wed Dec 14 04:31:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 5664 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 844EE23E01 for ; Wed, 14 Dec 2011 04:34:44 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7AAFAA183B9 for ; Wed, 14 Dec 2011 04:34:44 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id k10so61148eaa.11 for ; Tue, 13 Dec 2011 20:34:44 -0800 (PST) Received: by 10.204.157.12 with SMTP id z12mr210114bkw.18.1323837284275; Tue, 13 Dec 2011 20:34:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs101258bkc; Tue, 13 Dec 2011 20:34:44 -0800 (PST) Received: by 10.68.208.162 with SMTP id mf2mr1174452pbc.0.1323837281789; Tue, 13 Dec 2011 20:34:41 -0800 (PST) Received: from na3sys009aog121.obsmtp.com ([74.125.149.145]) by mx.google.com with SMTP id e10si5111228pbv.56.2011.12.13.20.34.35 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 20:34:41 -0800 (PST) Received-SPF: pass (google.com: domain of mturquette@ti.com designates 74.125.149.145 as permitted sender) client-ip=74.125.149.145; Authentication-Results: mx.google.com; spf=pass (google.com: domain of mturquette@ti.com designates 74.125.149.145 as permitted sender) smtp.mail=mturquette@ti.com Received: from mail-gy0-f172.google.com ([209.85.160.172]) (using TLSv1) by na3sys009aob121.postini.com ([74.125.148.12]) with SMTP ID DSNKTugnWzx0qguipsHP8+PdOw6PAyLnFILX@postini.com; Tue, 13 Dec 2011 20:34:39 PST Received: by mail-gy0-f172.google.com with SMTP id r16so360805ghr.31 for ; Tue, 13 Dec 2011 20:34:35 -0800 (PST) Received: by 10.236.77.72 with SMTP id c48mr8564815yhe.55.1323837275392; Tue, 13 Dec 2011 20:34:35 -0800 (PST) Received: from localhost.localdomain (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id v48sm2145601yhk.6.2011.12.13.20.34.32 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 20:34:34 -0800 (PST) From: Mike Turquette To: linux@arm.linux.org.uk Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khilman@ti.com, tony@atomide.com, b-cousson@ti.com, rnayak@ti.com, jeremy.kerr@canonical.com, paul@pwsan.com, broonie@opensource.wolfsonmicro.com, tglx@linutronix.de, linus.walleij@stericsson.com, amit.kucheria@linaro.org, dsaxena@linaro.org, patches@linaro.org, linaro-dev@lists.linaro.org, grant.likely@secretlab.ca, sboyd@quicinc.com, shawn.guo@freescale.com, skannan@quicinc.com, magnus.damm@gmail.com, arnd.bergmann@linaro.org, eric.miao@linaro.org, richard.zhao@linaro.org, mturquette@linaro.org, mturquette@ti.com, andrew@lunn.ch Subject: [PATCH 1/6] HACK: omap: opp: add fake 400MHz OPP to bypass MPU Date: Tue, 13 Dec 2011 20:31:23 -0800 Message-Id: <1323837088-2469-2-git-send-email-mturquette@ti.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323837088-2469-1-git-send-email-mturquette@ti.com> References: <1323837088-2469-1-git-send-email-mturquette@ti.com> The following patch is only for testing __clk_reparent as part of the new common struct clk stuff. It may make your board burst into flames or otherwise void various warrantees. This patch introduces a 400MHz OPP for the MPU, which happens to correspond to the bypass clk rate on the 4430 Panda (with 38.4MHz SYS_CLK). Using CPUfreq to set the MPU to this rate puts the MPU into Low Power Bypass, which triggers the __clk_reparent code in drivers/clk/clk.c, which migrates the dpll_mpu_ck directory (and all of its subdirs) to the div_mpu_hs_clk dir under dpll_core_ck. Not-signed-off-by: Mike Turquette --- arch/arm/mach-omap2/opp4xxx_data.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index 2293ba2..f1da758 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -68,6 +68,15 @@ struct omap_volt_data omap44xx_vdd_core_volt_data[] = { static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { /* MPU OPP1 - OPP50 */ OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV), + /* + * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI + * + * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE. After + * transitioning to this OPP you can see the migration in debugfs: + * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to + * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk + */ + OPP_INITIALIZER("mpu", true, 400000000, 1100000), /* MPU OPP2 - OPP100 */ OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV), /* MPU OPP3 - OPP-Turbo */