From patchwork Wed Jun 11 08:56:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 31719 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f197.google.com (mail-ve0-f197.google.com [209.85.128.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4ABDD203C2 for ; Wed, 11 Jun 2014 08:58:27 +0000 (UTC) Received: by mail-ve0-f197.google.com with SMTP id jz11sf21316239veb.4 for ; Wed, 11 Jun 2014 01:58:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=3u8Z1BFJxvgoQWIMYDpE1zbOjQpWD8BS8vzL8T7nqS0=; b=Y3rYMgclvCmz2kc4G9dQA2GkEMSCYMSsEALyzS5NQYF3KM5AerVh8You4hg+O1wOdC HfEenYQ2S47uNiMf7zE9e24UGzdL9ApE+GVaOJsVMFIrfVNYx4H4Teg1U/hdrBLiZtgX Zb1TI3r8DEVO1Vlu7sPe1I5no+LjxGuOq+iONOqJTq03UwfNlrt1SI6KGJNqtUmGsPKT 8CdIlq8SQ4nyF+V8ca8xZcJ2qiwltxbCTMAhsS8ow0K3kxaLqGle7FppfmeTNlFBEj0K VM+vzR8N1ucKgcr79fvaE55683Dfsy4eCZL6QFIALQO2sx0/Y5CmpjAX+OmLL/6xPFN6 rJ0Q== X-Gm-Message-State: ALoCoQkmXS/1GxdthXp1HseL9iurY3Grn6HtK7Fy6Ofo7MiU/0ugt1A64LyrTbZ6jDPU2XYyOiUO X-Received: by 10.236.209.97 with SMTP id r61mr8670219yho.33.1402477107024; Wed, 11 Jun 2014 01:58:27 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.96.201 with SMTP id k67ls2497551qge.22.gmail; Wed, 11 Jun 2014 01:58:26 -0700 (PDT) X-Received: by 10.221.4.66 with SMTP id ob2mr38110183vcb.28.1402477106888; Wed, 11 Jun 2014 01:58:26 -0700 (PDT) Received: from mail-ve0-f170.google.com (mail-ve0-f170.google.com [209.85.128.170]) by mx.google.com with ESMTPS id fw20si14014357vec.95.2014.06.11.01.58.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Jun 2014 01:58:26 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.170 as permitted sender) client-ip=209.85.128.170; Received: by mail-ve0-f170.google.com with SMTP id oz11so5643978veb.1 for ; Wed, 11 Jun 2014 01:58:26 -0700 (PDT) X-Received: by 10.220.59.65 with SMTP id k1mr37384658vch.22.1402477106754; Wed, 11 Jun 2014 01:58:26 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.54.6 with SMTP id vs6csp286447vcb; Wed, 11 Jun 2014 01:58:26 -0700 (PDT) X-Received: by 10.66.175.166 with SMTP id cb6mr11657999pac.128.1402477105875; Wed, 11 Jun 2014 01:58:25 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id kd3si37352792pbc.49.2014.06.11.01.58.25; Wed, 11 Jun 2014 01:58:25 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932264AbaFKI6A (ORCPT + 27 others); Wed, 11 Jun 2014 04:58:00 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59787 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932216AbaFKI54 (ORCPT ); Wed, 11 Jun 2014 04:57:56 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5B8vSgF004382; Wed, 11 Jun 2014 03:57:28 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5B8vSJZ020920; Wed, 11 Jun 2014 03:57:28 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 11 Jun 2014 03:57:27 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5B8uiSj020510; Wed, 11 Jun 2014 03:57:24 -0500 From: Roger Quadros To: , , CC: , , , , , , , , , Roger Quadros Subject: [PATCH 11/36] mtd: nand: omap: Update DT binding documentation Date: Wed, 11 Jun 2014 11:56:16 +0300 Message-ID: <1402477001-31132-12-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402477001-31132-1-git-send-email-rogerq@ti.com> References: <1402477001-31132-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add compatible id, interrupts and update reg property description. As the NAND controller needs access to GPMC register space, we need to pass a second memory resource to the NAND controller node. Due to the wierd way the reg property has been implemented (i.e. CS number required in 1st number of reg property) we will need to use a number outside the possible CS numbers for the GPMC register space. As a SoC can have fewer than 10 chip selects, 255 seems like a safe bet for the GPMC register space. Signed-off-by: Roger Quadros --- Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 5e1f31b..8831116 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -13,7 +13,13 @@ Documentation/devicetree/bindings/mtd/nand.txt Required properties: + - compatible: "ti,omap2-nand" - reg: The CS line the peripheral is connected to + Should contain 2 resource specifiers + - range id (CS number), base offset and length of the + NAND I/O space + - range id, base offset and length of the GPMC register space. + - interrupts: Interrupt resource specifier for GPMC interrupt. Optional properties: @@ -53,17 +59,21 @@ Example for an AM33xx board: gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; - reg = <0x50000000 0x1000000>; + reg = <0x50000000 0x36c>; interrupts = <100>; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; - ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000 /* CS0 space, 16MB */ + 255 0 0x50000000 0x36c>; /* GPMC reg space */ elm_id = <&elm>; nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + compatible = "ti,omap2-nand"; + reg = <0 0 4 /* CS0, offset 0, NAND I/O window 4 */ + 255 0 0x36c>; /* GPMC reg space */ + interrupts = <100>; nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; ti,nand-xfer-type = "polled";