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[209.132.180.67]) by mx.google.com with ESMTP id iq8si17626512pbc.93.2014.07.28.14.17.32 for ; Mon, 28 Jul 2014 14:17:33 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751981AbaG1VRb (ORCPT + 6 others); Mon, 28 Jul 2014 17:17:31 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:33652 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751389AbaG1VRa (ORCPT ); Mon, 28 Jul 2014 17:17:30 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6SLGnT1003023; Mon, 28 Jul 2014 16:16:49 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6SLGmYC014495; Mon, 28 Jul 2014 16:16:48 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Mon, 28 Jul 2014 16:16:48 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6SLGmA4002357; Mon, 28 Jul 2014 16:16:48 -0500 From: Felipe Balbi To: Tony Lindgren CC: Linux OMAP Mailing List , Linux ARM Kernel Mailing List , , , , , , , Linux Kernel Mailing List , Felipe Balbi Subject: [PATCH 03/35] arm: omap: irq: start to remove irq_banks array Date: Mon, 28 Jul 2014 16:15:51 -0500 Message-ID: <1406582183-696-4-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.0.1.563.g66f467c In-Reply-To: <1406582183-696-1-git-send-email-balbi@ti.com> References: <1406582183-696-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We have a single bank in that array, this patch is in preparation to remove that array. It just shifts everything to a new set of functions for register IO while also removing old ones. Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/irq.c | 64 ++++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 96073a2..83163d0 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -82,21 +82,20 @@ struct omap3_intc_regs { }; /* INTC bank register get/set */ - -static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) +static void intc_writel(u32 reg, u32 val) { - writel_relaxed(val, bank->base_reg + reg); + writel_relaxed(val, omap_irq_base + reg); } -static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) +static u32 intc_readl(u32 reg) { - return readl_relaxed(bank->base_reg + reg); + return readl_relaxed(omap_irq_base + reg); } /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(struct irq_data *d) { - intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); + intc_writel(INTC_CONTROL, 0x1); } static void omap_mask_ack_irq(struct irq_data *d) @@ -109,19 +108,19 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) { unsigned long tmp; - tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; + tmp = intc_readl(INTC_REVISION) & 0xff; pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); - tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); + tmp = intc_readl(INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ - intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); + intc_writel(INTC_SYSCONFIG, tmp); - while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) + while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) /* Wait for reset to complete */; /* Enable autoidle */ - intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); + intc_writel(INTC_SYSCONFIG, 1 << 0); } int omap_irq_pending(void) @@ -133,7 +132,7 @@ int omap_irq_pending(void) int irq; for (irq = 0; irq < bank->nr_irqs; irq += 32) - if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 + + if (intc_readl(INTC_PENDING_IRQ0 + ((irq >> 5) << 5))) return 1; } @@ -307,22 +306,20 @@ void omap_intc_save_context(void) { int ind = 0, i = 0; for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { - struct omap_irq_bank *bank = irq_banks + ind; intc_context[ind].sysconfig = - intc_bank_read_reg(bank, INTC_SYSCONFIG); + intc_readl(INTC_SYSCONFIG); intc_context[ind].protection = - intc_bank_read_reg(bank, INTC_PROTECTION); + intc_readl(INTC_PROTECTION); intc_context[ind].idle = - intc_bank_read_reg(bank, INTC_IDLE); + intc_readl(INTC_IDLE); intc_context[ind].threshold = - intc_bank_read_reg(bank, INTC_THRESHOLD); + intc_readl(INTC_THRESHOLD); for (i = 0; i < INTCPS_NR_IRQS; i++) intc_context[ind].ilr[i] = - intc_bank_read_reg(bank, (0x100 + 0x4*i)); + intc_readl((INTC_ILR0 + 0x4 * i)); for (i = 0; i < INTCPS_NR_MIR_REGS; i++) intc_context[ind].mir[i] = - intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + - (0x20 * i)); + intc_readl(INTC_MIR0 + (0x20 * i)); } } @@ -331,23 +328,16 @@ void omap_intc_restore_context(void) int ind = 0, i = 0; for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { - struct omap_irq_bank *bank = irq_banks + ind; - intc_bank_write_reg(intc_context[ind].sysconfig, - bank, INTC_SYSCONFIG); - intc_bank_write_reg(intc_context[ind].sysconfig, - bank, INTC_SYSCONFIG); - intc_bank_write_reg(intc_context[ind].protection, - bank, INTC_PROTECTION); - intc_bank_write_reg(intc_context[ind].idle, - bank, INTC_IDLE); - intc_bank_write_reg(intc_context[ind].threshold, - bank, INTC_THRESHOLD); + intc_writel(INTC_SYSCONFIG, intc_context[ind].sysconfig); + intc_writel(INTC_PROTECTION, intc_context[ind].protection); + intc_writel(INTC_IDLE, intc_context[ind].idle); + intc_writel(INTC_THRESHOLD, intc_context[ind].threshold); for (i = 0; i < INTCPS_NR_IRQS; i++) - intc_bank_write_reg(intc_context[ind].ilr[i], - bank, (0x100 + 0x4*i)); + intc_writel(INTC_ILR0 + 0x4 * i, + intc_context[ind].ilr[i]); for (i = 0; i < INTCPS_NR_MIR_REGS; i++) - intc_bank_write_reg(intc_context[ind].mir[i], - &irq_banks[0], INTC_MIR0 + (0x20 * i)); + intc_writel(INTC_MIR0 + 0x20 * i, + intc_context[ind].mir[i]); } /* MIRs are saved and restore with other PRCM registers */ } @@ -364,13 +354,13 @@ void omap3_intc_prepare_idle(void) * Disable autoidle as it can stall interrupt controller, * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) */ - intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); + intc_writel(INTC_SYSCONFIG, 0); } void omap3_intc_resume_idle(void) { /* Re-enable autoidle */ - intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG); + intc_writel(INTC_SYSCONFIG, 1); } asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)