From patchwork Tue Oct 18 07:55:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 77933 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp757415qge; Tue, 18 Oct 2016 00:56:11 -0700 (PDT) X-Received: by 10.99.122.17 with SMTP id v17mr2150100pgc.18.1476777371311; Tue, 18 Oct 2016 00:56:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fl4si23642199pab.94.2016.10.18.00.56.11; Tue, 18 Oct 2016 00:56:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932740AbcJRH4L (ORCPT + 4 others); Tue, 18 Oct 2016 03:56:11 -0400 Received: from arroyo.ext.ti.com ([198.47.19.12]:52849 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932489AbcJRH4K (ORCPT ); Tue, 18 Oct 2016 03:56:10 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u9I7te8c015948; Tue, 18 Oct 2016 02:55:40 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9I7tegN022083; Tue, 18 Oct 2016 02:55:40 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Tue, 18 Oct 2016 02:55:40 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9I7tYEh028694; Tue, 18 Oct 2016 02:55:38 -0500 From: Tero Kristo To: , , CC: Subject: [PATCH 2/7] ARM: DRA7: hwmod: Add data for AES IP Date: Tue, 18 Oct 2016 10:55:22 +0300 Message-ID: <1476777327-700-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476777327-700-1-git-send-email-t-kristo@ti.com> References: <1476777327-700-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Joel Fernandes DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kristo@ti.com: squash in support for both AES1 and AES2 cores] Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e89a7ec..4988a9e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -690,6 +690,50 @@ .parent_hwmod = &dra7xx_dss_hwmod, }; +/* AES (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = { + .rev_offs = 0x0080, + .sysc_offs = 0x0084, + .syss_offs = 0x0088, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_aes_hwmod_class = { + .name = "aes", + .sysc = &dra7xx_aes_sysc, + .rev = 2, +}; + +/* AES1 */ +static struct omap_hwmod dra7xx_aes1_hwmod = { + .name = "aes1", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* AES2 */ +static struct omap_hwmod dra7xx_aes2_hwmod = { + .name = "aes2", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'elm' class * @@ -2957,6 +3001,22 @@ static int dra7xx_pciess_reset(struct omap_hwmod *oh) .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> aes1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> aes2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { .master = &dra7xx_l4_per2_hwmod, @@ -3836,6 +3896,8 @@ static int dra7xx_pciess_reset(struct omap_hwmod *oh) &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, &dra7xx_l3_main_1__hdmi, + &dra7xx_l3_main_1__aes1, + &dra7xx_l3_main_1__aes2, &dra7xx_l4_per1__elm, &dra7xx_l4_wkup__gpio1, &dra7xx_l4_per1__gpio2,