From patchwork Fri Mar 21 05:52:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 26787 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f70.google.com (mail-pa0-f70.google.com [209.85.220.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 33E7020143 for ; Fri, 21 Mar 2014 05:55:07 +0000 (UTC) Received: by mail-pa0-f70.google.com with SMTP id lj1sf4795770pab.5 for ; Thu, 20 Mar 2014 22:55:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:message-id :reply-to:references:mime-version:content-type:content-disposition :in-reply-to:user-agent:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=cQ1AH0QIUJwWM7bqO4tOBBWWOeMDZlKHRcpW2bcFC0M=; b=f6TjUaNEDBdA+vyTXf8gu7dbtxCG4Ub7tzlbY21fw6Lm3ydbHdkgP+leQtITbW4RDz 5Pg7s0AYf8DRPQTkExrpvva9aEdGLZjI6QJOe/GOOCU2TEla8ARbr9/e3UpxP5Kc5EiB TX76zfP+6roa9emUUzv0OWKs2p/Y4MAG0nAuwvc9Zk2uPQWztYOjhzi/2azBz35Sj80V P5B/1uJcNwAGJ2Wrjl+qNelsAJWlRLeIlC/iBtYwW8TuuoWfVm90Sw9eDBtu/CeN4+Kl Pq6JtSw9CEbYi7wvcb5a2u4uCDWBd/LeH0hCAS3jcRm9cW1+1j4W+uxpo+VSkeHbVr0p JOBw== X-Gm-Message-State: ALoCoQn0mEtu0yg1V8kIP6rIqZAUa5TswdcHEmYxMZD7jaIqaVoFPgKTBfaVqVkjwA1UG9DPTsqK X-Received: by 10.66.188.238 with SMTP id gd14mr107365pac.18.1395381306955; Thu, 20 Mar 2014 22:55:06 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.39.133 with SMTP id v5ls512522qgv.23.gmail; Thu, 20 Mar 2014 22:55:06 -0700 (PDT) X-Received: by 10.52.26.161 with SMTP id m1mr19752275vdg.24.1395381306833; Thu, 20 Mar 2014 22:55:06 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id sj4si965709vdc.48.2014.03.20.22.55.06 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 22:55:06 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id la4so2124808vcb.3 for ; Thu, 20 Mar 2014 22:55:06 -0700 (PDT) X-Received: by 10.58.190.99 with SMTP id gp3mr6391639vec.32.1395381306713; Thu, 20 Mar 2014 22:55:06 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.78.9 with SMTP id i9csp6424vck; Thu, 20 Mar 2014 22:55:05 -0700 (PDT) X-Received: by 10.66.248.227 with SMTP id yp3mr51046359pac.116.1395381305131; Thu, 20 Mar 2014 22:55:05 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id mu18si2877089pab.190.2014.03.20.22.55.03; Thu, 20 Mar 2014 22:55:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752119AbaCUFzC (ORCPT + 9 others); Fri, 21 Mar 2014 01:55:02 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:48864 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750987AbaCUFzB (ORCPT ); Fri, 21 Mar 2014 01:55:01 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s2L5sUjm025421; Fri, 21 Mar 2014 00:54:30 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2L5sT4G018582; Fri, 21 Mar 2014 00:54:29 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Fri, 21 Mar 2014 00:54:29 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2L5sSSX012518; Fri, 21 Mar 2014 00:54:29 -0500 Date: Fri, 21 Mar 2014 00:52:42 -0500 From: Felipe Balbi To: Lokesh Vutla CC: , , , , , , , , , Dave Gerlach Subject: Re: [PATCH] ARM: dts: am437x-gp-evm: Do not reset gpio5 Message-ID: <20140321055242.GA1959@saruman.home> Reply-To: References: <1395379213-15451-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1395379213-15451-1-git-send-email-lokeshvutla@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On Fri, Mar 21, 2014 at 10:50:13AM +0530, Lokesh Vutla wrote: > From: Dave Gerlach > > Do not reset GPIO5 at boot-up because GPIO5_7 is used > on AM437x GP-EVM to control VTT regulators on DDR3. > Without this some GP-EVM boards will fail to boot because > of DDR3 corruption. > > Reported-by: Nishanth Menon > Tested-by: Nishanth Menon > Signed-off-by: Dave Gerlach > Signed-off-by: Lokesh Vutla every now and again we see a patch like this because yet another board is using a GPIO to toggle DDR regulators. Instead of constantly patching things like this, how about we try something like below (build-tested only): Then, we can even remove ti,no-reset flag from all GPIO DT nodes. diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 1f33f5d..f5962ff 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2610,6 +2610,10 @@ static int __init _setup_reset(struct omap_hwmod *oh) if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) return -EPERM; + /* NEVER reset GPIO blocks */ + if (strncmp(oh->name, "gpio", 4) == 0) + return 0; + if (oh->rst_lines_cnt == 0) { r = _enable(oh); if (r) { diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 4243190..ce8b53a 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -1130,6 +1130,29 @@ static void omap_gpio_chip_init(struct gpio_bank *bank) static const struct of_device_id omap_gpio_match[]; +static void omap_gpio_init_context(struct gpio_bank *p) +{ + struct omap_gpio_reg_offs *regs = p->regs; + void __iomem *base = p->base; + + p->context.ctrl = readl_relaxed(base + regs->ctrl); + p->context.oe = readl_relaxed(base + regs->direction); + p->context.wake_en = readl_relaxed(base + regs->wkup_en); + p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); + p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); + p->context.risingdetect = readl_relaxed(base + regs->risingdetect); + p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); + p->context.irqenable1 = readl_relaxed(base + regs->irqenable); + p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); + + if (regs->set_dataout && p->regs->clr_dataout) + p->context.dataout = readl_relaxed(base + regs->set_dataout); + else + p->context.dataout = readl_relaxed(base + regs->dataout); + + p->context_valid = true; +} + static int omap_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1246,6 +1269,7 @@ static int omap_gpio_probe(struct platform_device *pdev) omap_gpio_mod_init(bank); omap_gpio_chip_init(bank); omap_gpio_show_rev(bank); + omap_gpio_init_context(bank); pm_runtime_put(bank->dev); @@ -1325,8 +1349,6 @@ update_gpio_context_count: return 0; } -static void omap_gpio_init_context(struct gpio_bank *p); - static int omap_gpio_runtime_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -1466,29 +1488,6 @@ void omap2_gpio_resume_after_idle(void) } #if defined(CONFIG_PM_RUNTIME) -static void omap_gpio_init_context(struct gpio_bank *p) -{ - struct omap_gpio_reg_offs *regs = p->regs; - void __iomem *base = p->base; - - p->context.ctrl = readl_relaxed(base + regs->ctrl); - p->context.oe = readl_relaxed(base + regs->direction); - p->context.wake_en = readl_relaxed(base + regs->wkup_en); - p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); - p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); - p->context.risingdetect = readl_relaxed(base + regs->risingdetect); - p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); - p->context.irqenable1 = readl_relaxed(base + regs->irqenable); - p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); - - if (regs->set_dataout && p->regs->clr_dataout) - p->context.dataout = readl_relaxed(base + regs->set_dataout); - else - p->context.dataout = readl_relaxed(base + regs->dataout); - - p->context_valid = true; -} - static void omap_gpio_restore_context(struct gpio_bank *bank) { writel_relaxed(bank->context.wake_en,