From patchwork Mon Aug 21 23:48:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110604 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931649qge; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) X-Received: by 10.99.111.204 with SMTP id k195mr18772819pgc.20.1503359386508; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359386; cv=none; d=google.com; s=arc-20160816; b=m53YFPfi+Ir62B8qwrEGH5Mn7VyG3yKCg77qxGFcYhmEZe7+rHIAQZaQpl4vwDDPbz d5wUpiQjeIMmN8HAiVb7wMgHTAWH+OIq7y1Z5btZ0n1IwO7l+WT25wkJs8qB8wf9RgP4 NhzbPXcV7bYIucf35xzgvbHN+BThGetG4Z7K9Z+dv6WObIOV7v+GYbsXnFpAEKI4Nwqk lNicFgywldY26hgpEviTxCTvGgZuwgSskZ3ijS7pkuoraQEFyGxNKaPlTSXoBJIQUFcP DcRW7qj5IhamCiq8jnCfPviN6O+dDuSapHQy/BioDk1jDG4XwAuMiTwQXPUWJQcjgznq +7mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=DnUPfnEFMhyP6q35KJR3nDjxPKI5EqXgIRxjPE7MJJw=; b=GaZ1O+PYO1hgPknz71uOIFjNZQNdXp+SCxDm+Tz7vH/EtHVVFfa7LQIlRuvEogY8AY MSwBafHXKsNUyJKxNCvKVPbGcJqICv29w7NivXvQY35I3SjakaQwwyOzEhoUHgRzG0lS 1tvIreJ7TmJTgRDsFqVzSM44mtU6VrMpjOf9LEUGGh++4r8eIr0Y3xWmNDjcI+DF2XfA vH8c+4Ar04ic3dNFabr0HlLuNqU0A1tYPzKHEEek/P7yfvHqJoAILiQf1jR1uph+xwCk aC6f6iU2tqpLHBorBQx0NsxLq6pjvJCkTyPYw9gYFijK6tI/MXeiSMAkZVeZdKIxVpmp votA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jKk6+G2O; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.49.46; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jKk6+G2O; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754328AbdHUXtp (ORCPT + 3 others); Mon, 21 Aug 2017 19:49:45 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:54711 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754271AbdHUXto (ORCPT ); Mon, 21 Aug 2017 19:49:44 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmPbb013497; Mon, 21 Aug 2017 18:48:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359305; bh=0qDzSDVXgs6AVfWVCQAF5wQjn6FSrzZOWUrnB2uIlTg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jKk6+G2O7BvVyGI6cUxqUHwtP3eUEbvM9vQJDEI6QoWN/FojQorNn96TKIfoiQsJJ ktf4retpEuDSPomZjd4r3QPSOAWGgKaT5eBHNwxQdRWB/+3SnO9i/Ii+dKLOjjPRji VecSeMv33pA91s0P8cDoclff+rtLYtum/C/mCJw4= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKGo002265; Mon, 21 Aug 2017 18:48:20 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:20 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKPP031288; Mon, 21 Aug 2017 18:48:20 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307078; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 1/8] ARM: DRA7: hwmod data: Add MMU data for IPUs Date: Mon, 21 Aug 2017 18:48:11 -0500 Message-ID: <20170821234818.4755-2-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org A new MMU hwmod class and data structures are added for representing the MMUs within the IPU1 and IPU2 processor subsystems present on DRA7xx/AM57xx SoCs. Note that the clock integration is slightly different between IPU1 and IPU2. IPU2 functional clock is sourced directly from dpll_core_h22x2_ck, while IPU1 has a mux clock for which one of the inputs is dpll_core_h22x2_ck. This mux clock is configured to be sourced from the dpll_core_h22x2_ck in turn, so that both IPU1 and IPU2 run at the same clock frequency. This is already addressed in commit 39879c7d963e ("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL"). Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index f040244c57e7..bf55802448ac 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1800,6 +1800,69 @@ static struct omap_hwmod dra7xx_mmc4_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &dra7xx_mmu_sysc, +}; + +/* IPU MMUs */ +static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +/* mmu ipu1 */ +static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = { + .name = "mmu_ipu1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu ipu2 */ +static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = { + .name = "mmu_ipu2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'mpu' class * */ @@ -2901,6 +2964,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> mmu_ipu1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu_ipu2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l4_per1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -4010,6 +4089,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc2, &dra7xx_l4_per1__mmc3, &dra7xx_l4_per1__mmc4, + &dra7xx_l3_main_1__mmu_ipu1, + &dra7xx_l3_main_1__mmu_ipu2, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, &dra7xx_l4_cfg__ocp2scp3,