From patchwork Fri Mar 7 10:31:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 872070 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDB1F2116EC; Fri, 7 Mar 2025 10:32:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741343541; cv=none; b=jbMX5Zc8T4HkOeb4VihHyH8kjbEgYgs3KgEyi5iPLyBHVViJR7ts0jD/pUltWt3TwetvZZfRR84VbwQGj2bos0zi4t9TLSa12GsbT7ES9uyOKBavIykNvXc7Ga/RZNtjoKQL8PmjifQYo3Ikr2581wWoXah7OPNxT41dwELJKcY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741343541; c=relaxed/simple; bh=otfaJ0xMMeh/atsNLkGV1pQKe210EqmR07xww2LVZqg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u+34muXwEFwkXMH6WjK7cN14tWeQ5aYHijTlPcenRk31I7ZcAIhLoyi5lleAb4erJ5Tw6AFBu4oGWdMXgdM6DLcF9/yo5LMsFR/8Zhjy2WX2hGvu3bl9/d1RxBdxa/5YxRkOhdERlaEXuRvuSPN+k00dJF/AWwbzbX9NfuAnRyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=o/LtjNU6; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="o/LtjNU6" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 527AVrsd343912 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 7 Mar 2025 04:31:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1741343513; bh=gWdPIaObctAFLenCR68iVhRvFpVcjAdMR3Ra7YLkhsk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o/LtjNU6UtuYlYW3rP7wA4CE3z0/Bvfo/R1N3XIPoZ01XFeWHJdNsaEkuAiAFGwd9 txuGJZj47kBuHmV5YRj6iXgZkeuAJt4wPouN51d5Lr5BuypRIHWT1+oNe2XI7h3+Fl s7ldFUKj8qirdYgM8kWfQc0mC5hO8U3EJgeHgy6U= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 527AVrBY026836; Fri, 7 Mar 2025 04:31:53 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 7 Mar 2025 04:31:52 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 7 Mar 2025 04:31:52 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 527AVSQ6016876; Fri, 7 Mar 2025 04:31:48 -0600 From: Siddharth Vadapalli To: , , , , , , , , , , CC: , , , , , Subject: [PATCH 4/4] PCI: j721e: Add support to build as a loadable module Date: Fri, 7 Mar 2025 16:01:28 +0530 Message-ID: <20250307103128.3287497-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307103128.3287497-1-s-vadapalli@ti.com> References: <20250307103128.3287497-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea The 'pci-j721e.c' driver is the application/glue/wrapper driver for the Cadence PCIe Controllers on TI SoCs. Implement support for building it as a loadable module. Signed-off-by: Siddharth Vadapalli --- drivers/pci/controller/cadence/Kconfig | 6 ++-- drivers/pci/controller/cadence/pci-j721e.c | 37 ++++++++++++++++++++-- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 82b58096eea0..72d7d264d6c3 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP different vendors SoCs. config PCI_J721E - bool + tristate config PCI_J721E_HOST - bool "TI J721E PCIe controller (host mode)" + tristate "TI J721E PCIe controller (host mode)" depends on ARCH_K3 || COMPILE_TEST depends on OF select PCIE_CADENCE_HOST @@ -57,7 +57,7 @@ config PCI_J721E_HOST core. config PCI_J721E_EP - bool "TI J721E PCIe controller (endpoint mode)" + tristate "TI J721E PCIe controller (endpoint mode)" depends on ARCH_K3 || COMPILE_TEST depends on OF depends on PCI_ENDPOINT diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 0341d51d6aed..0900e7dd6ac7 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) #define ENABLE_REG_SYS_2 0x108 +#define ENABLE_CLR_REG_SYS_2 0x308 #define STATUS_REG_SYS_2 0x508 #define STATUS_CLR_REG_SYS_2 0x708 #define LINK_DOWN BIT(1) @@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) return IRQ_HANDLED; } +static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie) +{ + u32 reg; + + reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2); + reg |= pcie->linkdown_irq_regfield; + j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg); +} + static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) { u32 reg; @@ -632,9 +643,27 @@ static void j721e_pcie_remove(struct platform_device *pdev) struct j721e_pcie *pcie = platform_get_drvdata(pdev); struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; struct device *dev = &pdev->dev; + struct cdns_pcie_ep *ep; + struct cdns_pcie_rc *rc; + + if (pcie->mode == PCI_MODE_RC) { + rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie); + cdns_pcie_host_disable(rc); + } else { + ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie); + cdns_pcie_ep_disable(ep); + } + + if (pcie->reset_gpio) { + msleep(PCIE_T_PVPERL_MS); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + } + + if (pcie->refclk) + clk_disable_unprepare(pcie->refclk); - clk_disable_unprepare(pcie->refclk); cdns_pcie_disable_phy(cdns_pcie); + j721e_pcie_disable_link_irq(pcie); pm_runtime_put(dev); pm_runtime_disable(dev); } @@ -729,4 +758,8 @@ static struct platform_driver j721e_pcie_driver = { .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), }, }; -builtin_platform_driver(j721e_pcie_driver); +module_platform_driver(j721e_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCIe controller driver for TI's J721E and related SoCs"); +MODULE_AUTHOR("Kishon Vijay Abraham I ");