From patchwork Thu Apr 10 13:27:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 28188 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f197.google.com (mail-ie0-f197.google.com [209.85.223.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D770E212DC for ; Thu, 10 Apr 2014 13:27:45 +0000 (UTC) Received: by mail-ie0-f197.google.com with SMTP id rd18sf18178156iec.8 for ; Thu, 10 Apr 2014 06:27:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:cc:subject:references:in-reply-to:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe :content-type:content-transfer-encoding; bh=sHPruyShSPQQuRh2qi3t+smWJKf0FTkUgVZ1FmrX7DM=; b=W9S9Y8D0xe6natY35f6MDK/av33Wr96s5M52X6+vrq1FBucil815sZ7G/l31a4+n1u uez3Ef+dsLokjeuoTMrj4oBKLAD32yVtlv2TiEkP+6H4LDZloO9ZMkiQPCI6w/HBIokg OGoFEATEbGDxBLrhsAW6O3SYdPHO6m19O0pDIdYwwKBa02/PVhjbj8Ut2TUzQuOp3Yi4 TcZxBmMVXtWQjthIch35P1Q48WTFU1xMs9GyLvQPdfShfKLgy+blbNwMRArC7TU3EuIW rnpUVX32QaDqpcHqrRv3Y88RYVRnYiqYB2abCJs1c84g8iBvIQEhWdckezpHTKDkuexs Of/Q== X-Gm-Message-State: ALoCoQlWB19Z4lkK2XLL/Xyx1OgaJMSzZvBsKX8rjP1JGoxR7KsU1BClllKoH6T7KWF0WO5v42dZ X-Received: by 10.182.28.36 with SMTP id y4mr8209821obg.46.1397136465258; Thu, 10 Apr 2014 06:27:45 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.106.202 with SMTP id e68ls1167890qgf.12.gmail; Thu, 10 Apr 2014 06:27:45 -0700 (PDT) X-Received: by 10.58.111.163 with SMTP id ij3mr802276veb.26.1397136465109; Thu, 10 Apr 2014 06:27:45 -0700 (PDT) Received: from mail-vc0-f177.google.com (mail-vc0-f177.google.com [209.85.220.177]) by mx.google.com with ESMTPS id f17si692105vcq.93.2014.04.10.06.27.45 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Apr 2014 06:27:45 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.177; Received: by mail-vc0-f177.google.com with SMTP id if17so3312227vcb.36 for ; Thu, 10 Apr 2014 06:27:45 -0700 (PDT) X-Received: by 10.52.0.193 with SMTP id 1mr12303478vdg.0.1397136464986; Thu, 10 Apr 2014 06:27:44 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp59283vcb; Thu, 10 Apr 2014 06:27:44 -0700 (PDT) X-Received: by 10.66.140.104 with SMTP id rf8mr19448266pab.107.1397136464093; Thu, 10 Apr 2014 06:27:44 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id wt1si2202903pbc.376.2014.04.10.06.27.43; Thu, 10 Apr 2014 06:27:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030800AbaDJN1m (ORCPT + 5 others); Thu, 10 Apr 2014 09:27:42 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:59071 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030658AbaDJN1j (ORCPT ); Thu, 10 Apr 2014 09:27:39 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3ADR7xm019898; Thu, 10 Apr 2014 08:27:07 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3ADR7CB024105; Thu, 10 Apr 2014 08:27:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Thu, 10 Apr 2014 08:27:07 -0500 Received: from [172.24.190.153] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3ADR5nS031943; Thu, 10 Apr 2014 08:27:06 -0500 Message-ID: <53469C29.8050906@ti.com> Date: Thu, 10 Apr 2014 18:57:05 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Russell King - ARM Linux CC: Tony Lindgren , Linux OMAP Mailing List , Linux ARM Mailing List Subject: Re: [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support References: <20140404101808.GG27282@n2100.arm.linux.org.uk> <53440D73.6060504@ti.com> <20140409162327.GH27282@n2100.arm.linux.org.uk> <534686DF.7070207@ti.com> <20140410120348.GK27282@n2100.arm.linux.org.uk> <53468B8E.9040604@ti.com> In-Reply-To: <53468B8E.9040604@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nsekhar@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On Thursday 10 April 2014 05:46 PM, Sekhar Nori wrote: > This will work. NS_LOCKDOWN is required for L2C-220 as well and so I was > thinking about adding a new l2c220_enable() which will set the > NS_LOCKDOWN and then call l2c_enable() Here is a patch for what I was saying above. --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index c47ac8f..dc9e03b 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -105,6 +105,8 @@ #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) #define L2X0_AUX_CTRL_ASSOC_SHIFT 13 #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) +/* L2C-220/310 common bits */ +#define L2C_AUX_CTRL_NS_LOCKDOWN BIT(26) /* L2C-210 specific bits */ #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) @@ -113,7 +115,6 @@ #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) #define L220_AUX_CTRL_FWA_SHIFT 23 #define L220_AUX_CTRL_FWA_MASK (3 << 23) -#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) /* L2C-310 specific bits */ #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ @@ -122,7 +123,6 @@ #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ -#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) #define L310_AUX_CTRL_NS_INT_CTRL BIT(27) #define L310_AUX_CTRL_DATA_PREFETCH BIT(28) #define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 6b2a056..34cafe0 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -216,8 +216,6 @@ int __init omap4_l2_cache_init(void) { /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ u32 aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | - L310_AUX_CTRL_NS_LOCKDOWN | - L310_AUX_CTRL_NS_INT_CTRL | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b1f103d..b6af13f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -498,11 +498,23 @@ static void l2c220_sync(void) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } +static void __init l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) +{ + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L2C_AUX_CTRL_NS_LOCKDOWN; + + l2c_enable(base, aux, num_lock); +} + static const struct l2c_init_data l2c220_data = { .type = "L2C-220", .way_size_0 = SZ_8K, .num_lock = 1, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range, @@ -764,7 +776,7 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); } - l2c_enable(base, aux, num_lock); + l2c220_enable(base, aux, num_lock); if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); @@ -1027,7 +1039,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = { .way_size_0 = SZ_8K, .num_lock = 1, .of_parse = l2x0_of_parse, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range,