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Tue, 20 Dec 2022 08:02:48 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 20 Dec 2022 08:02:48 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Tue, 20 Dec 2022 08:02:44 -0800 From: Sumit Gupta To: , , , , , , , , , , CC: , , , , Subject: [Patch v1 00/10] Tegra234 Memory interconnect support Date: Tue, 20 Dec 2022 21:32:30 +0530 Message-ID: <20221220160240.27494-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT070:EE_|BL0PR12MB4849:EE_ X-MS-Office365-Filtering-Correlation-Id: cb6e7447-9baa-408d-60ff-08dae2a3a5b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2022 16:02:51.3148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb6e7447-9baa-408d-60ff-08dae2a3a5b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4849 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch series adds memory interconnect support for Tegra234 SoC. It is used to dynamically scale DRAM Frequency as per the bandwidth requests from different Memory Controller (MC) clients. MC Clients use ICC Framework's icc_set_bw() api to dynamically request for the DRAM bandwidth (BW). As per path, the request will be routed from MC to the EMC driver. EMC driver will then send the Client ID, type, and frequency request info to the BPMP-FW which will set the final DRAM freq considering all exisiting requests. MC and EMC are the ICC providers. Nodes in path for a request will be: Client[1-n] -> MC -> EMC -> EMEM/DRAM The patch series also adds interconnect support in the CPUFREQ driver for scaling bandwidth with CPU frequency. For that, added per cluster OPP table in the CPUFREQ driver and using that to scale DRAM freq by requesting the minimum BW respective to the given CPU frequency in OPP table for that cluster. Sumit Gupta (10): memory: tegra: add interconnect support for DRAM scaling in Tegra234 memory: tegra: adding iso mc clients for Tegra234 memory: tegra: add pcie mc clients for Tegra234 memory: tegra: add support for software mc clients in Tegra234 dt-bindings: tegra: add icc ids for dummy MC clients arm64: tegra: Add cpu OPP tables and interconnects property cpufreq: Add Tegra234 to cpufreq-dt-platdev blocklist cpufreq: tegra194: add OPP support and set bandwidth memory: tegra: get number of enabled mc channels memory: tegra: make cluster bw request a multiple of mc_channels arch/arm64/boot/dts/nvidia/tegra234.dtsi | 276 +++++++++++ drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra194-cpufreq.c | 152 +++++- drivers/memory/tegra/mc.c | 80 +++- drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra186-emc.c | 166 +++++++ drivers/memory/tegra/tegra234.c | 565 ++++++++++++++++++++++- include/dt-bindings/memory/tegra234-mc.h | 5 + include/soc/tegra/mc.h | 11 + include/soc/tegra/tegra-icc.h | 79 ++++ 10 files changed, 1312 insertions(+), 24 deletions(-) create mode 100644 include/soc/tegra/tegra-icc.h