From patchwork Wed Mar 27 08:18:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 783980 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8339724A08; Wed, 27 Mar 2024 08:20:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711527619; cv=none; b=XSBzmdw22Zt+gq9ZMH5rF0qBCnhZBTwZRbRd1W6mbHBx+7ceEeUUENYEeOlEbfEfY0QLoOivrh+UEgffK6FIH0f4o/JnkrpmELveeYq8kst0Xxm0g2wZvpQVVG3JUdZ54hWy5kDt2KtTJK6Qrnc6alD4GsT9hbOiWWoy9YAlV8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711527619; c=relaxed/simple; bh=4/FAYLTXQmjxdLbvd49UrSfamwGUSPPlHwFEhSJo3Vk=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=JMIOkh0gBK/VdSRVZ1okzq17hrwP46oZQcIJfWPLzWHSt/GKu97K5/1TI/xLsY8ihEeKiFkyWXQS/ew5QSLGg58t2+Fif8FoCtEuRShiLmne3UrsfRKY8sO7AD4xVmMhGiafm/Kw4VKLYKgwJJE2tBLzBrdtfn+zorNrfwx6VSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YP/y5dru; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YP/y5dru" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42R50LET014007; Wed, 27 Mar 2024 08:20:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=b1Dw41b QyXMFzFQyeT2fXuDbkes6K0mKY6009FjYA4A=; b=YP/y5druxh4iYbL1iEjAxxV uaP1kHvKk3ITRsy6w9kbzVQxELJkin15wegn6twHhGcbTXoQKOK4DByYeJLZIcg9 cTkTrkdPFavN2sjDXat8YySl4yWCb+9vz0jk7J/7G4KtKOrWvyLiaSXGvRyoJ905 NkFT+e4Abjfj6rOqU6a5wchpJgHnUGnDhS6YkssKNYbV54VngKcGk0mXzA7mYjs0 BeXgc4PV46SdzNZiTELU8VtgXnvx09p1Ur3kNkMTJ36icULKyKvbO7CMdCleQ8Ms 4TKDR96kYUkUndDTPoMckZKFc7GqpRwZwooyFE5jiW3ud0JDLC/c97KtzC1i++g= = Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x4784h3xk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 27 Mar 2024 08:20:12 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42R8KBa0011202 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 27 Mar 2024 08:20:11 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 27 Mar 2024 01:20:06 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC Date: Wed, 27 Mar 2024 13:48:47 +0530 Message-ID: <20240327081850.2924870-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nw6eIpLXHyDwPKBeEnbQC2t5bRa8E0vL X-Proofpoint-ORIG-GUID: nw6eIpLXHyDwPKBeEnbQC2t5bRa8E0vL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-27_04,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403270054 MSM platforms manage NoC related clocks and scaling from RPM. However, in IPQ SoCs, RPM is not involved in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for the accessing the peripherals present in the system. Hence add a minimalistic interconnect driver that establishes a path from the processor/memory to those peripherals and vice versa. --- v4: gcc-ipq9574.c Use clk_hw instead of indices common.c Do icc register in qcom_cc_probe() call stream common.h Add icc clock info to qcom_cc_desc structure v3: qcom,ipq9574.h Move 'first id' define to clock driver gcc-ipq9574.c: Use indexed identifiers here to avoid confusion Fix error messages and move code to common.c as it can be shared with future SoCs v2: qcom,ipq9574.h Fix license identifier Rename macros qcom,ipq9574-gcc.yaml Include interconnect-cells gcc-ipq9574.c Update commit log Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig ipq9574.dtsi Moved to separate patch Include interconnect-cells to clock controller node drivers/clk/qcom/Kconfig: Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK Varadarajan Narayanan (3): dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: add IPQ9574 interconnect clocks support arm64: dts: qcom: ipq9574: Add icc provider ability to gcc .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 + drivers/clk/qcom/Kconfig | 2 + drivers/clk/qcom/common.c | 34 ++++++++++- drivers/clk/qcom/common.h | 4 +- drivers/clk/qcom/gcc-ipq9574.c | 54 +++++++++++++++++ .../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++ 7 files changed, 156 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h