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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000013C.mail.protection.outlook.com (10.167.244.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Fri, 15 Mar 2024 03:39:14 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 14 Mar 2024 22:38:33 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v5 0/8] AMD Pstate Driver Core Performance Boost Date: Fri, 15 Mar 2024 11:38:01 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013C:EE_|SA1PR12MB8842:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e905fde-67f4-4f8d-654e-08dc44a17c22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:14.2195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e905fde-67f4-4f8d-654e-08dc44a17c22 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8842 Hi all, The patchset series add core performance boost feature for AMD pstate driver including passisve ,guide and active mode support. User can change core frequency boost control with a new sysfs entry: "/sys/devices/system/cpu/amd_pstate/cpb_boost" The legancy boost interface has been removed due to the function conflict with new cpb_boost which can support all modes. 1). enable core boost: $ sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" $ lscpu -ae CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ 0 0 0 0 0:0:0:0 yes 4201.0000 400.0000 2983.578 1 0 0 1 1:1:1:0 yes 4201.0000 400.0000 2983.578 2 0 0 2 2:2:2:0 yes 4201.0000 400.0000 2583.855 3 0 0 3 3:3:3:0 yes 4201.0000 400.0000 2983.578 4 0 0 4 4:4:4:0 yes 4201.0000 400.0000 2983.578 2). disabble core boost: $ sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" $ lscpu -ae 0 0 0 0 0:0:0:0 yes 5759.0000 400.0000 2983.578 1 0 0 1 1:1:1:0 yes 5759.0000 400.0000 2983.578 2 0 0 2 2:2:2:0 yes 5759.0000 400.0000 2983.578 3 0 0 3 3:3:3:0 yes 5759.0000 400.0000 2983.578 4 0 0 4 4:4:4:0 yes 5759.0000 400.0000 2983.578 The patches have been tested with the AMD 7950X processor and many users would like to get core boost control enabled for power saving. If you would like to test this patchset, it needs to apply the patchset based on below one latest version patchset. https://lore.kernel.org/lkml/20240208102122.GAZcSrIkbPJfIExdF6@fat_crate.local/ Perry. Changes from v4: * move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h * pick RB flag from Gautham R. Shenoy * add Cc Oleksandr Natalenko * rebase to latest linux-pm/bleeding-edge branch * rebase the patch set on top of [PATCH v7 0/6] AMD Pstate Fixes And Enhancements * update [PATCH v7 2/6] to use MSR_K7_HWCR_CPB_DIS_BIT Changes from v3: * rebased to linux-pm/bleeding-edge v6.8 * rename global to amd_pstate_global_params(Oleksandr Natalenko) * remove comments for boot_supported in amd_pstate.h * fix the compiler warning for amd-pstate-ut.ko * use for_each_online_cpu in cpb_boost_store which fix the null pointer error during testing * fix the max frequency value to be KHz when cpb boost disabled(Gautham R. Shenoy) Changes from v2: * move global struct to amd-pstate.h * fix the amd-pstate-ut with new cpb control interface Changes from v1: * drop suspend/resume fix patch 6/7 because of the fix should be in another fix series instead of CPB feature * move the set_boost remove patch to the last(Mario) * Fix commit info with "Closes:" (Mario) * simplified global.cpb_supported initialization(Mario) * Add guide mode support for CPB control * Fixed some Doc typos and add guide mode info to Doc as well. v1: https://lore.kernel.org/all/cover.1706255676.git.perry.yuan@amd.com/ v2: https://lore.kernel.org/lkml/cover.1707047943.git.perry.yuan@amd.com/ v3: https://lore.kernel.org/lkml/cover.1707297581.git.perry.yuan@amd.com/ v4: https://lore.kernel.org/lkml/cover.1710322310.git.perry.yuan@amd.com/ *** BLURB HERE *** Perry Yuan (8): cpufreq: acpi: move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h cpufreq: amd-pstate: initialize new core precision boost state cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control cpufreq: amd-pstate: fix max_perf calculation for amd_get_max_freq() cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Documentation: cpufreq: amd-pstate: introduce the new cpu boost control method cpufreq: amd-pstate: remove legacy set_boost callback for passive mode cpufreq: amd-pstate-ut: support new cpb boost control interface Documentation/admin-guide/pm/amd-pstate.rst | 11 ++ arch/x86/include/asm/msr-index.h | 2 + drivers/cpufreq/acpi-cpufreq.c | 2 - drivers/cpufreq/amd-pstate-ut.c | 2 +- drivers/cpufreq/amd-pstate.c | 157 +++++++++++++++----- include/linux/amd-pstate.h | 15 +- 6 files changed, 150 insertions(+), 39 deletions(-)