From patchwork Thu Sep 9 14:38:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thermal-bot for Lad Prabhakar X-Patchwork-Id: 508587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BB66C433EF for ; Thu, 9 Sep 2021 14:46:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6E40961101 for ; Thu, 9 Sep 2021 14:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244780AbhIIOry (ORCPT ); Thu, 9 Sep 2021 10:47:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343879AbhIIOrp (ORCPT ); Thu, 9 Sep 2021 10:47:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E32EAC06122F for ; Thu, 9 Sep 2021 07:38:36 -0700 (PDT) Date: Thu, 09 Sep 2021 14:38:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1631198315; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4I+63PVzAnTJo3Z3/uXn62y4/ZaZiQauFvwxTpIoGY0=; b=NEjTqJGpI4Vxnh0L/eMBw+ja81kxaCDACLj6oknA6ZGABr6lzWLBHMUQWjl1kF8dLIEdLm gofFUzmXKm9XzyLI4PI4uhLyHUBF8se3nuqMUEtmCfFpcTsZhp6+nn7HdGh73pyzUMkSUk 9Wm/XX211vSi1PUZHuvHeT73sluOu/vq4eTKvB/aWNdYrV8diIjHhFxj+0NMyNQ8LgBmBw 9Vo+2eo1ejU0DS9M6avEQj0xEvj5apOJrhqpPssYot3kCOXMl3IkTmSHDKqVyK8dUt1orK L0MLa2DhhUB46mSyQRBqaGuCk4C27dLXKrX2ybLbKaRvE7KVJcPe+u2DPmZY9w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1631198315; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4I+63PVzAnTJo3Z3/uXn62y4/ZaZiQauFvwxTpIoGY0=; b=xXsbqCetf5WVygeonFF1cXcpVMYtWM5w/rBugGNt4MKyDZz+bZ4/cVcDItm1glf0elrUBz BHuW8vYMy64iQMAg== From: "thermal-bot for Thara Gopinath" Sender: tip-bot2@linutronix.de Reply-to: linux-pm@vger.kernel.org To: linux-pm@vger.kernel.org Subject: [thermal: thermal/next] dt-bindings: thermal: Add dt binding for QCOM LMh Cc: Thara Gopinath , Rob Herring , Daniel Lezcano , rui.zhang@intel.com, amitk@kernel.org In-Reply-To: <20210809191605.3742979-8-thara.gopinath@linaro.org> References: <20210809191605.3742979-8-thara.gopinath@linaro.org> MIME-Version: 1.0 Message-ID: <163119831481.25758.15294576140462455549.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The following commit has been merged into the thermal/next branch of thermal: Commit-ID: 0284b52e85341e3cd4b70c8b2423fd23b8a003a8 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git//0284b52e85341e3cd4b70c8b2423fd23b8a003a8 Author: Thara Gopinath AuthorDate: Mon, 09 Aug 2021 15:16:05 -04:00 Committer: Daniel Lezcano CommitterDate: Wed, 18 Aug 2021 17:53:37 +02:00 dt-bindings: thermal: Add dt binding for QCOM LMh Add dt binding documentation to describe Qualcomm Limits Management Hardware node. Signed-off-by: Thara Gopinath Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20210809191605.3742979-8-thara.gopinath@linaro.org --- Documentation/devicetree/bindings/thermal/qcom-lmh.yaml | 82 ++++++++- 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml new file mode 100644 index 0000000..289e9a8 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Limits Management Hardware(LMh) + +maintainers: + - Thara Gopinath + +description: + Limits Management Hardware(LMh) is a hardware infrastructure on some + Qualcomm SoCs that can enforce temperature and current limits as + programmed by software for certain IPs like CPU. + +properties: + compatible: + enum: + - qcom,sdm845-lmh + + reg: + items: + - description: core registers + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + cpus: + description: + phandle of the first cpu in the LMh cluster + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,lmh-temp-arm-millicelsius: + description: + An integer expressing temperature threshold at which the LMh thermal + FSM is engaged. + + qcom,lmh-temp-low-millicelsius: + description: + An integer expressing temperature threshold at which the state machine + will attempt to remove frequency throttling. + + qcom,lmh-temp-high-millicelsius: + description: + An integer expressing temperature threshold at which the state machine + will attempt to throttle the frequency. + +required: + - compatible + - reg + - interrupts + - '#interrupt-cells' + - interrupt-controller + - cpus + - qcom,lmh-temp-arm-millicelsius + - qcom,lmh-temp-low-millicelsius + - qcom,lmh-temp-high-millicelsius + +additionalProperties: false + +examples: + - | + #include + + lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0x17d70800 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + };