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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , Steven Rostedt , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v7 01/14] x86/cpufeatures: Add AMD Collaborative Processor Performance Control feature flag Date: Fri, 24 Dec 2021 09:04:55 +0800 Message-ID: <20211224010508.110159-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211224010508.110159-1-ray.huang@amd.com> References: <20211224010508.110159-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b545ed3f-319e-4784-f584-08d9c6797dab X-MS-TrafficTypeDiagnostic: BL1PR12MB5126:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kr8VmuVJ84+Bgyfl6uhznLhM+TlWh+JYpS2wuWb1vqB0R6J0MaWG+RB+N69NR+88aoNRzJZDzSdNdmpJSigGr4CdGACZ3w5D6LT+N7wN7Y/xTU/wYVvLrq548PoXwIPLViaEyLwTVCW8Y1YzM91Jfv4BBsNsZtnKgcbxlnoqnwoNvrVOf6iMnqSZRAbtjBAn8FSgx83lEfnUc91qq2TRDVGPbm69c4V9B8LhhRFei2LZKYRHKbChAJHMUF2uuj8KUZqBhcyb/5K8cCN8v54VpuBY3M7S3mrjvcNJ8h6pTL58I0QChhc35+NRVZB8Jo5gQ7Koz4Gm4XuLXG62omQ6J1K59aQT3LbGejZrr11f4BiigcBRBM5NTug5ac5r9a1cq71E908sEoLZc/6ntOV/WzToXtbGFfGP2A9O5ViAer55IpHxarCKYmOXERxAfn02SWKkI0UIrMXuWSzjJIgvLgAoDwcMiqNA2UURS6z0t+SUwKx0XDLtz+8HVynzM07+401U72Ho/N4ZMBP8U3/pgFMmdk5pF76nUDyx86VQ7k8pV7+lOZ/0ttgl89D7ABD4DZBjJgDd7tb8Qrc/q8Ets0WOJDuoLggckHTfX6Agp9Sg/ZUcjopI/Gd7m4l/U+gR1H+4xqI/TqAJubVmu6Ye0tNaIOnWVLX2S0XcOKU45fH6glQbZZiKsMbrwSt2VyV7lzFMR7IAu/edqJKRYbT9+Zi+dxCkW+WVmeET74rmDHSzuhlF+ohqQ03jzZM4ZIG2fdDflfo2cmiC2xz2uuYyw0u0034KJJX2oA2W4KRLs7Q= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700002)(336012)(36756003)(186003)(316002)(16526019)(7696005)(54906003)(6666004)(110136005)(508600001)(2616005)(40460700001)(5660300002)(1076003)(2906002)(70206006)(70586007)(81166007)(82310400004)(47076005)(86362001)(356005)(36860700001)(426003)(7416002)(8936002)(8676002)(4326008)(26005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2021 01:05:35.0306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b545ed3f-319e-4784-f584-08d9c6797dab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5126 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add Collaborative Processor Performance Control feature flag for AMD processors. This feature flag will be used on the following AMD P-State driver. The AMD P-State driver has two approaches to implement the frequency control behavior. That depends on the CPU hardware implementation. One is "Full MSR Support" and another is "Shared Memory Support". The feature flag indicates the current processors with "Full MSR Support". Acked-by: Borislav Petkov Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d5b5f2ab87a0..18de5f76f198 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */