From patchwork Sun Dec 4 05:59:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6846C47090 for ; Sun, 4 Dec 2022 05:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229983AbiLDF7h (ORCPT ); Sun, 4 Dec 2022 00:59:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229990AbiLDF71 (ORCPT ); Sun, 4 Dec 2022 00:59:27 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A3FE1A396 for ; Sat, 3 Dec 2022 21:59:24 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id l8so9928711ljh.13 for ; Sat, 03 Dec 2022 21:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6jyq4dFoSz2Fyu1tkmi8RjA5wzVwQNYzG7qMhqzsEhY=; b=IBIjHUMKT0Px1VwdY8au5Xb/X+OSAvXGbxVn9l5v2d9lrfglNUOaLbv3ORyNrs8L0e hdSQrmz+G1wL+6D7nJSlUVsK52XWv8TyRQingZE4XSclfSO4tWmXwrtvbVWuWu0YFDKU q/gYjarOQOr/NoTbfbPCdpYT3V2S024pUOSTv5Phbtbcea9Oa074Cfu7RyyeACBFl/q/ sIB+H4crSDX7f2TqOu+NPs4/4/pt95E1yp109m9dX/71oaLlXCjxxFCNN2wwDJrvYwux EAz3gGsT1SdBa4wHBJ/WnNaMsdERMWXmYzDB7TDU2jVf8BSlWFLWPl1fTq08OYUuVD6d M5WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6jyq4dFoSz2Fyu1tkmi8RjA5wzVwQNYzG7qMhqzsEhY=; b=4OXSADxGN8XzgMGiGwDg7+Kx9q3p5pnNzzI7jra5shM75MzsUMYxsyIyos/CRVbb3s XLSEVg2UffZG8VcTcLaf+awuUjwumobZVqiW0DQo1ZVroyKfRKzJtubFIHPIrvEzmPTM Ck6CeBCECqLEd9RQGUX4N1zcFvuNUPlL57N1thGLoVIcYqWAZ3zor+/wS22bDW+xYxBG 89QEQ3JOJpTRQZuNRLHZDOebuPDiU/HpD1FsTta5YGw+07K9oQy92lTQHRSlsIzAw/aG sCK109w+s1uxA0A9ch/bVXikmjq8refJnzKbFCgoYIVRQodVRleuxiZJ9Pc4fA5DM6nj Jx5Q== X-Gm-Message-State: ANoB5pklNw8y/bMgU+9NCGjBEcCX1muydFMtX4BAvR8liG1rvHPyS109 d/TGgM2BsaSAOmPI2VCNRnI33g== X-Google-Smtp-Source: AA0mqf4x8p5GePF77GvBStQz8mGuwQQa4L+vqLRX5P9a6xfcZBK465jP/JUXH9in/B41CwWNnk/Cew== X-Received: by 2002:a2e:3309:0:b0:279:d1ef:69f7 with SMTP id d9-20020a2e3309000000b00279d1ef69f7mr4609659ljc.167.1670133562416; Sat, 03 Dec 2022 21:59:22 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o6-20020a05651205c600b004917a30c82bsm1650028lfo.153.2022.12.03.21.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Dec 2022 21:59:22 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 15/15] ARM: dts: qcom-apq8084: specify per-sensor calibration cells Date: Sun, 4 Dec 2022 07:59:09 +0200 Message-Id: <20221204055909.1351895-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221204055909.1351895-1-dmitry.baryshkov@linaro.org> References: <20221204055909.1351895-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8084.dtsi | 262 +++++++++++++++++++++++++++- 1 file changed, 256 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a..f0f788ac38f0 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,209 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + tsens_s0_p1: s0_p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + tsens_s1_p1: s1_p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + tsens_s2_p1: s2_p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + tsens_s3_p1: s3_p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + tsens_s4_p1: s4_p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + tsens_s5_p1: s5_p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + tsens_s6_p1: s6_p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + tsens_s7_p1: s7_p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + tsens_s8_p1: s8_p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + tsens_s9_p1: s9_p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + tsens_s0_p2: s0_p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + tsens_s1_p2: s1_p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + tsens_s2_p2: s2_p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + tsens_s3_p2: s3_p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + tsens_s4_p2: s4_p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + tsens_s5_p2: s5_p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + tsens_s6_p2: s6_p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + tsens_s7_p2: s7_p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + tsens_s8_p2: s8_p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + tsens_s9_p2: s9_p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + tsens_s5_p2_backup: s5_p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + tsens_s6_p2_backup: s6_p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + tsens_s7_p2_backup: s7_p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + tsens_s8_p2_backup: s8_p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + tsens_s9_p2_backup: s9_p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + tsens_s0_p1_backup: s0_p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + tsens_s1_p1_backup: s1_p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + tsens_s2_p1_backup: s2_p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + tsens_s3_p1_backup: s3_p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + tsens_s4_p1_backup: s4_p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + tsens_s5_p1_backup: s5_p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + tsens_s6_p1_backup: s6_p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + tsens_s7_p1_backup: s7_p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + tsens_s8_p1_backup: s8_p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + tsens_s9_p1_backup: s9_p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + tsens_s0_p2_backup: s0_p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + tsens_s1_p2_backup: s1_p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + tsens_s2_p2_backup: s2_p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + tsens_s3_p2_backup: s3_p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + tsens_s4_p2_backup: s4_p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +459,60 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow";