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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20515542498sm2056065ad.188.2024.08.28.20.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 20:39:43 -0700 (PDT) From: Nick Hu To: greentime.hu@sifive.com, zong.li@sifive.com, "Rafael J. Wysocki" , Pavel Machek , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Andrew Jones , Conor Dooley , Samuel Holland , Nick Hu , Sunil V L , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] time-riscv: Stop stimecmp when cpu hotplug Date: Thu, 29 Aug 2024 11:39:00 +0800 Message-Id: <20240829033904.477200-3-nick.hu@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829033904.477200-1-nick.hu@sifive.com> References: <20240829033904.477200-1-nick.hu@sifive.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Stop the stimecmp when the cpu is going to be off otherwise the timer interrupt may pending while performing power down operation. Signed-off-by: Nick Hu --- drivers/clocksource/timer-riscv.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 48ce50c5f5e6..9a6acaa8dfb0 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -32,15 +32,19 @@ static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); static bool riscv_timer_cannot_wake_cpu; +static void riscv_clock_stop_stimecmp(void) +{ + csr_write(CSR_STIMECMP, ULONG_MAX); + if (IS_ENABLED(CONFIG_32BIT)) + csr_write(CSR_STIMECMPH, ULONG_MAX); +} + static void riscv_clock_event_stop(void) { - if (static_branch_likely(&riscv_sstc_available)) { - csr_write(CSR_STIMECMP, ULONG_MAX); - if (IS_ENABLED(CONFIG_32BIT)) - csr_write(CSR_STIMECMPH, ULONG_MAX); - } else { + if (static_branch_likely(&riscv_sstc_available)) + riscv_clock_stop_stimecmp(); + else sbi_set_timer(U64_MAX); - } } static int riscv_clock_next_event(unsigned long delta, @@ -126,7 +130,11 @@ static int riscv_timer_starting_cpu(unsigned int cpu) static int riscv_timer_dying_cpu(unsigned int cpu) { - disable_percpu_irq(riscv_clock_event_irq); + if (static_branch_likely(&riscv_sstc_available)) + riscv_clock_stop_stimecmp(); + else + disable_percpu_irq(riscv_clock_event_irq); + return 0; }