From patchwork Thu Sep 19 08:28:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 829777 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18B6A1990D6; Thu, 19 Sep 2024 08:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726734689; cv=none; b=dNdM17R7Mo1DdUlKhTnewKU24I3wreX0gWze/LZaJzIEWeprsYEsSsRSVxnV6mCZhxzp9V9se8PNMn0B1mlObIedJKQDRZ1qXszV0IUSgYM7GwsIlPvK+QwxZDjek6rX3Ab2KJ2f6oJp60aFhDNCg/ThgCY21NvLIWVOCGpjvFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726734689; c=relaxed/simple; bh=JaX6wUQ/bm9BHvP0cV2N11OE/HxkvRDSqS/WSD4Kw/s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HxA3GBRTu+FIXTrl+LxaCKp+reG9/Z0QGvfTsZXy+QR1VAAgllK/JKQvdlwjQBRr5n/iHwqlG5qqHrmr/emL2zkc59T9pT1GYK3UILsE5tpDzOg0QwBv9bmlWANFNAMZVF35PyxK47EkrkIcGahIy6/cBXWfIJqg3kXXDG9L/78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SitOQZYT; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SitOQZYT" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48J8VMmu012254; Thu, 19 Sep 2024 03:31:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1726734682; bh=ml7WXD4lYp/d/pZxmhToN7EUNx5OBXnZ8x8r4tbqS1Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SitOQZYTcGzye30dGESKfp2eoTEUXBjIPmHG9eWBwJ0kPx5dGrr6Du0cuFB0rOFIT LPona4kTcjvaVpHdcN5YmynP8Pqp1E8dYtdGKqxL+zQE+ywE6fVOnaXl7n/vL5BdAf waoHTXEy4WFDWxMT42QSu8LRn1OXrE/ZKVbwkOtM= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48J8VMqZ077614; Thu, 19 Sep 2024 03:31:22 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 19 Sep 2024 03:31:21 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 03:31:21 -0500 Received: from lcpd911.dhcp.ti.com (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48J8UrgZ042798; Thu, 19 Sep 2024 03:31:18 -0500 From: Dhruva Gole To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viresh Kumar , "Rafael J . Wysocki" CC: , , , , Dhruva Gole , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof Subject: [PATCH V4 4/6] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Date: Thu, 19 Sep 2024 13:58:08 +0530 Message-ID: <20240919082809.174589-5-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240919082809.174589-1-d-gole@ti.com> References: <20240919082809.174589-1-d-gole@ti.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Bryan Brattlof The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP table to enable this frequency [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 3efa12bb7254..7f3dc39e12bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock";