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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBE.mail.protection.outlook.com (10.167.243.184) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 17:15:38 +0000 Received: from AUS-P9-MLIMONCI.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 12:15:35 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta , Eric Naim , Peter Jung Subject: [PATCH v4 5/5] x86/amd: Use heterogeneous core topology for identifying boost numerator Date: Fri, 25 Oct 2024 12:14:59 -0500 Message-ID: <20241025171459.1093-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025171459.1093-1-mario.limonciello@amd.com> References: <20241025171459.1093-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBE:EE_|PH0PR12MB8029:EE_ X-MS-Office365-Filtering-Correlation-Id: d29b2044-9045-4a65-245f-08dcf518a552 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: S4nEfaduS0sc1bPMPbK4IZt4E53ogdkkttYGDgohzVc60jBvhBv2SLTcYkd34QFJpPyCYSWDr2JDsros/WCNO7a/Fm0ZEDlQwebbkrq93BQbsHnME0ZCJQsxMB0VhFihIxwZtpQuL6r4jIm7+Z3e4bBw1XbyBrE3jyaadar141WA6wRRfzC081m+LP3NE/DQzm7NZQXpfPFFEKtkTAP2pDMLm1fnaRWaMQsRldM+Dg7GZ3Db7eVEexp68HSVq7YjBBu+o2dkFtc3grxFxdWG8EU1bDnr2Ygdo4wdp3nbmueseYuYqrhdBIoxuwMtFjJ4BavvCJU+AxP1pCLOvf6FutvoMh0wLHawq/NxK7Vp80OVw4MpCsrRsGNSuaV7tH0SMoTaYAj9A2NDsBJlknFQLdq1NEeBq7YjmuLp2UUVO7hX+bgpLGfrm5vGDCDSQutozlS0u9W7tTOzUTuaLMEfbuWm45326VGDTRq/X2FiSd8PwOzWfSZyHehpZ/7WbHTh8uI9h9gufZSmN44fTphI6JMvjfX5QSynkINPWOZrt4AVjXBHaOHIEdzSMWq4+P8lZawx2VbB/X+2Z1iliKUVj/L2aFg+QCg5f+2BrQYKLPkuYxJe5H+PEEaFYQ+tAs6LJzZkDs3n7faq2Ma0uk7teYjBLERuiW3Ao5bN1/REpq+rUipPQ6gOsStHPAKlN11umKCNJ+IaJRQn6huyj6OizDC9G6J63SkFs7/QBg/ioWA4mDJmfh9C8Bif+GFSuZ6mzJmH9m6+w3Fg4wdnEggEQpjFPuuUATMV226IeLwYbJjvUkFlFsZJNpTBytpb4xPkxgZWwANB5pNYvdhbiOyX4pBHgg4tc70OyNqdf7Ncyn55X5fNAjptdCzCq5229ahVBvJk36lV+u8PbtXou2t+K+SsN9dhKzubMHj6rodjl+UFE3R4T34byme0jtIoVrTsx4BIgaAoFpAwugKgB9jwZnmookXSRcX5zIWpQyGQh7+vFuNz/64GNDogS6vKvfS/Uza6MN2s7llvJMafioL8vQ1S7Xo2KxOhGwYqKMS//XSDXDdBDR9S0qoqLzEAzzv7S3aYxmJUl90JhTsOgpy6cIhkidiO/LZTrOamKXjaLZ0Ugq6ls2KNSw/a5YQRI1th70ZT8PaGB6P+lI3zufaO0crxg/m9aZ6ftIIowkiCITZdAAP1VWwQeBdQ4k0zJQg1KzbANL6ZLmKVfP6oqOzNoqKO2nwsWXfrNxu5775RuSrHTzagifZcFgUqz5FWsgHwP2nkbvsjtZwKvy5GeBT8F3i2yIvH5rcdPFf/OF0iToi/tw6qfME0HCScKNaZdD/z21VDxd3nnb5bHAkUbKlZthHJo8JvjO2bvNKoKrtxwNFXch8i+Xo3a972y8ahFip8K/Xe+Ys21S99g0HH9U2qMQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 17:15:38.0630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d29b2044-9045-4a65-245f-08dcf518a552 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8029 AMD heterogeneous designs include two types of cores: * Performance * Efficiency Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency. X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026. On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings. Tested-by: Eric Naim Tested-by: Peter Jung Suggested-by: Perry Yuan Signed-off-by: Mario Limonciello --- v3->v4: * Drop default case and show warning in unknown case if hetero cores were detected (Boris) * Change get_topology_generic_cpu_type to get_topology_cpu_type (Mario) * Only performance boost numerator to hetero designs. This fixes an issue on Zen5 9950X which supports the CPUID for identifying core types but only has performance cores (Peter Jung) --- arch/x86/kernel/acpi/cppc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 956984054bf30..59edf64ad9edc 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -234,8 +234,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { + enum x86_topology_cpu_type core_type = get_topology_cpu_type(&cpu_data(cpu)); bool prefcore; int ret; + u32 tmp; ret = amd_detect_prefcore(&prefcore); if (ret) @@ -261,6 +263,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) break; } } + + /* detect if running on heterogeneous design */ + if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) { + switch (core_type) { + case TOPO_CPU_TYPE_UNKNOWN: + pr_warn("Undefined core type found for cpu %d\n", cpu); + break; + case TOPO_CPU_TYPE_PERFORMANCE: + /* use the max scale for performance cores */ + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE; + return 0; + case TOPO_CPU_TYPE_EFFICIENCY: + /* use the highest perf value for efficiency cores */ + ret = amd_get_highest_perf(cpu, &tmp); + if (ret) + return ret; + *numerator = tmp; + return 0; + } + } + *numerator = CPPC_HIGHEST_PERF_PREFCORE; return 0;