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[209.132.180.67]) by mx.google.com with ESMTP id y5si12475283pfe.184.2018.04.23.23.08.32; Mon, 23 Apr 2018 23:08:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hlVN8hmh; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756215AbeDXGIc (ORCPT + 11 others); Tue, 24 Apr 2018 02:08:32 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:38644 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756208AbeDXGIb (ORCPT ); Tue, 24 Apr 2018 02:08:31 -0400 Received: by mail-pf0-f193.google.com with SMTP id o76so6644303pfi.5 for ; Mon, 23 Apr 2018 23:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=QPYUFVe/J7/9TPuQp6Me7vBNCuwLOG0dwd89n7auLzM=; b=hlVN8hmhARxxEXYV9X52+bpt5JD+S0SqjUig86+v1B7xaK6uhKuaHtm4FgT9Tgayl4 fO+Dcx5bJiqFhTDQKF4lyZ4a+22CuBaMbphWa4WxosuzU2j/3FUUclVkCV9IWAPXNp4s Je185/lm/euPOi4cLc48MnGWsjOeLMq0P/dtI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=QPYUFVe/J7/9TPuQp6Me7vBNCuwLOG0dwd89n7auLzM=; b=Xw3bHPr5LDZWFW1SVJpBXpuuVFnxOgs1HAlxJtgX6AQlA2STtuASA0goGfLKwZ7Mid xr0gHVcdhQNR8mSIiKkiem+TF+FYWz6PEQhjEdkbJgW01OM3xuy/hbX/6KUPCQGFMCKh UnLEjus9sMIlIWq7Z/jahd1ycspmrwyURChpzsy/GT64MATybGt3FKw+MhhwPgGeE8l1 tgRBp4WUoNCi/l+SEpHM5kCNxOdjUcZW5i66CyDEVR0rhTWznRiHSKrlhZL6FuaZcAJv Pr4Xdryx1tHQBEtSJcu3+vdAdXHnRXu98kAgUquJKj+wX4bE47rnCxZwFKhK/AvHZ0NF UEHQ== X-Gm-Message-State: ALQs6tDH4+zP8jQ+sEGgZ29WW6n0Bn/kyNPiESP7P7LX3zyxxMhRW71p FMTQwV6vzCAsVBGx7Dn5H23fLg== X-Received: by 2002:a17:902:aa46:: with SMTP id c6-v6mr23027708plr.154.1524550110977; Mon, 23 Apr 2018 23:08:30 -0700 (PDT) Received: from localhost ([122.172.61.40]) by smtp.gmail.com with ESMTPSA id r81sm28706474pfj.79.2018.04.23.23.08.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Apr 2018 23:08:30 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , Miquel Raynal , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 3/3] cpufreq: add suspend/resume support in Armada 37xx DVFS driver Date: Tue, 24 Apr 2018 11:37:36 +0530 Message-Id: <4ca19364ff10083c3912ce428207c3f713f973b9.1524549644.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Miquel Raynal Add suspend/resume hooks in Armada 37xx DVFS driver to handle S2RAM operations. As there is currently no 'driver' structure, create one to store both the regmap and the register values during suspend operation. A syscore_ops is used to export the suspend/resume hooks. Signed-off-by: Miquel Raynal Signed-off-by: Viresh Kumar --- V1->V2: - Updated patch based on cpufreq-dt suspend/resume hooks. drivers/cpufreq/armada-37xx-cpufreq.c | 67 +++++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 2 deletions(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c index 9dafb3bbc334..c827d2437246 100644 --- a/drivers/cpufreq/armada-37xx-cpufreq.c +++ b/drivers/cpufreq/armada-37xx-cpufreq.c @@ -23,6 +23,8 @@ #include #include +#include "cpufreq-dt.h" + /* Power management in North Bridge register set */ #define ARMADA_37XX_NB_L0L1 0x18 #define ARMADA_37XX_NB_L2L3 0x1C @@ -56,6 +58,16 @@ */ #define LOAD_LEVEL_NR 4 +struct armada37xx_cpufreq_state { + struct regmap *regmap; + u32 nb_l0l1; + u32 nb_l2l3; + u32 nb_dyn_mod; + u32 nb_cpu_load; +}; + +static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state; + struct armada_37xx_dvfs { u32 cpu_freq_max; u8 divider[LOAD_LEVEL_NR]; @@ -136,7 +148,7 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, clk_set_parent(clk, parent); } -static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base) +static void armada37xx_cpufreq_disable_dvfs(struct regmap *base) { unsigned int reg = ARMADA_37XX_NB_DYN_MOD, mask = ARMADA_37XX_NB_DFS_EN; @@ -162,8 +174,44 @@ static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base) regmap_update_bits(base, reg, mask, mask); } +static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy) +{ + struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state; + + regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1); + regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3); + regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD, + &state->nb_cpu_load); + regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod); + + return 0; +} + +static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy) +{ + struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state; + + /* Ensure DVFS is disabled otherwise the following registers are RO */ + armada37xx_cpufreq_disable_dvfs(state->regmap); + + regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1); + regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3); + regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD, + state->nb_cpu_load); + + /* + * NB_DYN_MOD register is the one that actually enable back DVFS if it + * was enabled before the suspend operation. This must be done last + * otherwise other registers are not writable. + */ + regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod); + + return 0; +} + static int __init armada37xx_cpufreq_driver_init(void) { + struct cpufreq_dt_platform_data pdata; struct armada_37xx_dvfs *dvfs; struct platform_device *pdev; unsigned long freq; @@ -213,6 +261,15 @@ static int __init armada37xx_cpufreq_driver_init(void) goto put_clk; } + armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state), + GFP_KERNEL); + if (!armada37xx_cpufreq_state) { + ret = -ENOMEM; + goto put_clk; + } + + armada37xx_cpufreq_state->regmap = nb_pm_base; + armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); clk_put(clk); @@ -228,7 +285,11 @@ static int __init armada37xx_cpufreq_driver_init(void) /* Now that everything is setup, enable the DVFS at hardware level */ armada37xx_cpufreq_enable_dvfs(nb_pm_base); - pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + pdata.suspend = armada37xx_cpufreq_suspend; + pdata.resume = armada37xx_cpufreq_resume; + + pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata, + sizeof(pdata)); ret = PTR_ERR_OR_ZERO(pdev); if (ret) goto disable_dvfs; @@ -243,6 +304,8 @@ static int __init armada37xx_cpufreq_driver_init(void) freq = cur_frequency / dvfs->divider[load_lvl]; dev_pm_opp_remove(cpu_dev, freq); } + + kfree(armada37xx_cpufreq_state); put_clk: clk_put(clk); return ret;