From patchwork Fri Jul 1 08:20:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D9F5C43334 for ; Fri, 1 Jul 2022 08:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233158AbiGAIWr (ORCPT ); Fri, 1 Jul 2022 04:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234723AbiGAIWB (ORCPT ); Fri, 1 Jul 2022 04:22:01 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AE6F70E65 for ; Fri, 1 Jul 2022 01:21:35 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id r66so1784513pgr.2 for ; Fri, 01 Jul 2022 01:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bNEnKpORd3QNjxmd6zUBrP8J5Frzy4cYVk636zNrdD0=; b=NInfjvO3HxDbJt56x0UYfx+nwvC1lR93+qkcsX05NDwK5rNzTDLLw03Y/CGBpgN+0F 42bNNL8xJYwDLGgG/Ykhb8FwLm9q44K+YQeq6yGhoul+TvAZIvJZ7fQBSlgtSReLl3hU UrohJgZTbFVwxMOKGPQND7n6nVnq9+w0OMtzOM42N5ghKCaZN1xZ26FNFO61XNMS8jtc BfouMkbIzHbqaFMUQ0VLJub2rcav1Tnbg61uO893IIz0TTAd/So5sl/RDnLNuponV8Xn JQls62z6q0j1+ZvbzjXnFLzpiXo9QPhYOkKiSEq1lrbPT8fdvwRte6cDj0li4Wkh9Xp4 0V7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bNEnKpORd3QNjxmd6zUBrP8J5Frzy4cYVk636zNrdD0=; b=HqnRHeRGFaDP5dB6hzUvRcCnPjSYiI0uYcgcQXLN/+5pDYRQXxBIa36OyKpm40swWd BxadMESNi3JMQd9OAfKGj7V0Tce8MLYqoAAQASrP+ZEbhbIkeZtT/9ATZ3POMWKW6Xu/ csD8jdmX3U6g6erSn7ASY6nJ/GVnK1qxsen1NQm0Rx7Laclv2ArVdRXbicUDTRDvvQTX CjzX3xvLBmlp0kmRmXZhG608MNceSiHX7dE9NHUD5OpBQbVKmcRgB8lZOlyUdN5u9pdT 1RyJYdXgQyaG5JUlIEidjaRHx6JKpOldi6zvaJj8nrMek5xwE8gMvWgnkN7WnCQswIBW 5Auw== X-Gm-Message-State: AJIora9a613DxoGc3j3RihFOsWk9z5p83TRMcW2+mBmqzjkt36yqLWAf HHZg07KqgSwjk5CkbROTyoSzag== X-Google-Smtp-Source: AGRyM1uYcdqOf+57d5/HlFxYYKsxbNuIuRKJ9aqdI/aVgWcgYUkw2wQLaX4vKBZMZrBpE8TsLtScWA== X-Received: by 2002:a05:6a00:a12:b0:527:dba9:c416 with SMTP id p18-20020a056a000a1200b00527dba9c416mr15334406pfh.33.1656663695136; Fri, 01 Jul 2022 01:21:35 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id o12-20020a170902d4cc00b0016a3f9e4865sm15039024plg.148.2022.07.01.01.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:21:34 -0700 (PDT) From: Viresh Kumar To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: Viresh Kumar , linux-pm@vger.kernel.org, Vincent Guittot , "Rafael J. Wysocki" , Stephen Boyd , Nishanth Menon , Dmitry Osipenko , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH V2 18/30] memory: tegra: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:13 +0530 Message-Id: <74e3e4c6f63ea155aebd1c113d99e39bc2f8fd80.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Tested-by: Dmitry Osipenko Signed-off-by: Viresh Kumar --- drivers/memory/tegra/tegra124-emc.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 908f8d5392b2..8da6baa4c369 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1395,15 +1395,18 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc) static int tegra_emc_opp_table_init(struct tegra_emc *emc) { u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); - struct opp_table *hw_opp_table; - int err; + int opp_token, err; + struct dev_pm_opp_config config = { + .supported_hw = &hw_version, + .supported_hw_count = 1, + }; - hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); - err = PTR_ERR_OR_ZERO(hw_opp_table); - if (err) { - dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); + err = dev_pm_opp_set_config(emc->dev, &config); + if (err < 0) { + dev_err(emc->dev, "failed to set OPP config: %d\n", err); return err; } + opp_token = err; err = dev_pm_opp_of_add_table(emc->dev); if (err) { @@ -1430,7 +1433,7 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) remove_table: dev_pm_opp_of_remove_table(emc->dev); put_hw_table: - dev_pm_opp_put_supported_hw(hw_opp_table); + dev_pm_opp_clear_config(opp_token); return err; }