From patchwork Thu Jan 5 04:25:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 6057 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6750B23E01 for ; Thu, 5 Jan 2012 04:27:24 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 5D594A18261 for ; Thu, 5 Jan 2012 04:27:24 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so115813eaa.11 for ; Wed, 04 Jan 2012 20:27:24 -0800 (PST) Received: by 10.205.120.14 with SMTP id fw14mr174919bkc.53.1325737644169; Wed, 04 Jan 2012 20:27:24 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs391022bkc; Wed, 4 Jan 2012 20:27:23 -0800 (PST) Received: by 10.42.162.197 with SMTP id z5mr365000icx.48.1325737642702; Wed, 04 Jan 2012 20:27:22 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id g8si31551517ick.49.2012.01.04.20.27.22 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 20:27:22 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by mail-iy0-f178.google.com with SMTP id f6so340275iag.37 for ; Wed, 04 Jan 2012 20:27:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=srEGIjI+KibNmXd+3xDckaqwJ/gu55T0uYLVerSCbQs=; b=sOuQ6vZe64JrEteZ9LNsSOpblT/x58P7KQaEZavWRrR0cqtxfpNhOTCVpvDyU4Dgew hYxGpE8XwGZGOsJWXH9m6lfv7D8qq8hcXnCTwjnrSTPPdOPXXkFayqoepquypPIjaWqa uojYd/xBhTudYt06mLvjBjNl7e3GnuHoJYSD8= Received: by 10.50.108.140 with SMTP id hk12mr981930igb.18.1325737642028; Wed, 04 Jan 2012 20:27:22 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id rc7sm121098773igb.0.2012.01.04.20.27.19 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 20:27:21 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V5 3/5] ARM: exynos: save L2 settings during bootup Date: Thu, 5 Jan 2012 09:55:23 +0530 Message-Id: <1325737525-12869-4-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1325737525-12869-1-git-send-email-amit.kachhap@linaro.org> References: <1325737525-12869-1-git-send-email-amit.kachhap@linaro.org> This patch adds code to save L2 register configuration at boot, and later used to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/common.c | 42 ++++++++++++++++++++++++++++++---------- 1 files changed, 31 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index ba4ab1f..f8bb808 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -26,10 +26,12 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -451,20 +453,38 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); + + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + } l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);