From patchwork Tue Feb 21 06:19:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 6852 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EAEEB23EB0 for ; Tue, 21 Feb 2012 06:21:50 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id AC249A185A5 for ; Tue, 21 Feb 2012 06:21:50 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id z7so11912584iab.11 for ; Mon, 20 Feb 2012 22:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:dkim-signature:sender:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=+gtRV/JgLYTRe/Yxb7G30Tv9Y7Zc9/ZD8vgXgiYeu90=; b=t9Hl/aJxqiC5K1t2wdBZ9gK/Vf1RH10nNMwO19sHhPvNK+uGRkYvEvJcKRfDgrICu0 9dwbe9Kyc+mMNvvrcGD5Zi2SkY08Eiy1WveXpUmGfOrA6axvcMgYPCfRSCLoAAGND954 MIit5LhHGhBNbBoFkfRULLkrXZUiTULoOJRUM= MIME-Version: 1.0 Received: by 10.43.52.74 with SMTP id vl10mr20053831icb.55.1329805310481; Mon, 20 Feb 2012 22:21:50 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10csp80755ibr; Mon, 20 Feb 2012 22:21:50 -0800 (PST) Received: by 10.68.138.167 with SMTP id qr7mr59871624pbb.0.1329805309702; Mon, 20 Feb 2012 22:21:49 -0800 (PST) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id h6si23059882pbn.214.2012.02.20.22.21.48 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:49 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.50 as permitted sender) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.50 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass header.i=@gmail.com Received: by mail-pz0-f50.google.com with SMTP id d2so5431210dal.37 for ; Mon, 20 Feb 2012 22:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=+gtRV/JgLYTRe/Yxb7G30Tv9Y7Zc9/ZD8vgXgiYeu90=; b=XH7K1qGRNKHEAyWUEI/sI/b9nRM1sjwC/m3yzCYKjBnBzAhg9kfl2E2ehBiQGphv5e tWiZg6GtY+XpxB0nyA/qRj9wJ+xwP+p+L4X4XHGY8P0pgLp8J0QrBB0ucPj6vribOAG6 9CqQPcrnc4EpNZLEtBr1AsCLOKNdSrmY6ncgk= Received: by 10.68.243.144 with SMTP id wy16mr58447681pbc.35.1329805308902; Mon, 20 Feb 2012 22:21:48 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id vy2sm7541182pbb.48.2012.02.20.22.21.46 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:48 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V6 3/5] ARM: exynos: save L2 settings during bootup Date: Tue, 21 Feb 2012 11:49:48 +0530 Message-Id: <1329805190-8874-4-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> X-Gm-Message-State: ALoCoQlxkkmYTXS2I3TRhCqzLCg+iXiPDwVQ3iEIbgZXbRjR2xeA59kcZsbvUFXcSWAF0/wLDBx8 This patch adds code to save L2 register configuration at boot, and later used to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/common.c | 42 ++++++++++++++++++++++++++++++---------- 1 files changed, 31 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c59e188..9ff38aa 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -26,10 +26,12 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -441,20 +443,38 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); + + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + } l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);