From patchwork Tue Jan 22 08:25:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 14207 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B1BA423E02 for ; Tue, 22 Jan 2013 08:25:21 +0000 (UTC) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by fiordland.canonical.com (Postfix) with ESMTP id 4611CA18495 for ; Tue, 22 Jan 2013 08:25:21 +0000 (UTC) Received: by mail-vc0-f172.google.com with SMTP id l6so5350852vcl.31 for ; Tue, 22 Jan 2013 00:25:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=MrQk9ORGoUuYaCBKuIuwzYfYb3pC4+83tg9qmNRVFtE=; b=jCuE4HI+U3l7Q/p86R9Rpzaw3HNBGSDiadg/g4JZznJ3Wcj9Y5lJBL3xQak3OvLRqr meIZSF6KgLQTPr5zc//9cpP2+yPwTeGTLaxQTC9htkgBm87/oVFO6+jVsTz9YzykG16e OJrpEUPRfzI9hBgMrZn0D4m+sk7aVktfBfMzIFMp3i8xAKHUDJ2yvcCHDn9AjQJW+sNb aWe7kPZHwwcoF/nbZrlDf0ziJbLwL716Q/Stn1Yqd7Px/11wnUu3qbuR0SqZpGSPMGqQ iDXts/myu0kqZ/BeYN1FTy+TE/9UmMNLxU2rFX4qzQCzDco21aC9Hs+lOH4egAD4JpqF KQ8w== X-Received: by 10.220.209.74 with SMTP id gf10mr22323494vcb.10.1358843120768; Tue, 22 Jan 2013 00:25:20 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp239444veb; Tue, 22 Jan 2013 00:25:20 -0800 (PST) X-Received: by 10.68.219.164 with SMTP id pp4mr37099256pbc.72.1358843119365; Tue, 22 Jan 2013 00:25:19 -0800 (PST) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by mx.google.com with ESMTPS id j9si16587400pay.86.2013.01.22.00.25.18 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 22 Jan 2013 00:25:19 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.44 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.210.44; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.44 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by mail-da0-f44.google.com with SMTP id z20so3113575dae.31 for ; Tue, 22 Jan 2013 00:25:18 -0800 (PST) X-Received: by 10.68.234.36 with SMTP id ub4mr37369464pbc.68.1358843118549; Tue, 22 Jan 2013 00:25:18 -0800 (PST) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id i5sm10979835pax.13.2013.01.22.00.25.15 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 22 Jan 2013 00:25:17 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH] arm: plat-samsung: check soc ids before l2x0 cache restoration in resume Date: Tue, 22 Jan 2013 13:55:09 +0530 Message-Id: <1358843109-11072-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQk/bQE8vuTa7+CRksXLpSLcCMAukQxEuuOiMWxmmR4KGzBIY0Uz9rNf7lMw5iGWpuUpSWMc Only exynos4 based platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh --- arch/arm/mach-exynos/common.c | 2 ++ arch/arm/plat-samsung/include/plat/pm.h | 1 + arch/arm/plat-samsung/s5p-sleep.S | 28 ++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index cdaa55f..ab7ca00 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -796,6 +796,8 @@ static int __init exynos4_l2x0_cache_init(void) if (soc_is_exynos5250() || soc_is_exynos5440()) return 0; + s5p_cpu = samsung_cpu_id & EXYNOS4_CPU_MASK; + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); if (!ret) { l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 887a0c9..285c8c8 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -190,3 +190,4 @@ extern void samsung_pm_save_gpios(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); +extern unsigned long s5p_cpu; diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dad..006d35f 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,15 @@ #include #include +#define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4212_CPU_ID 0x43220000 +#define EXYNOS4412_CPU_ID 0xE4412200 +#define EXYNOS4_CPU_MASK 0xFFFE0000 + +#define EXYNOS4210_CPU (EXYNOS4210_CPU_ID & EXYNOS4_CPU_MASK) +#define EXYNOS4212_CPU (EXYNOS4212_CPU_ID & EXYNOS4_CPU_MASK) +#define EXYNOS4412_CPU (EXYNOS4412_CPU_ID & EXYNOS4_CPU_MASK) + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +60,22 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + adr r0, s5p_cpu + ldr r1, [r0] + + ldr r0, =EXYNOS4210_CPU + cmp r1, r0 + beq continue + + ldr r0, =EXYNOS4212_CPU + cmp r1, r0 + beq continue + + ldr r0, =EXYNOS4412_CPU + cmp r1, r0 + bne resume_l2on + +continue: adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE] @@ -77,4 +102,7 @@ ENDPROC(s3c_cpu_resume) .globl l2x0_regs_phys l2x0_regs_phys: .long 0 + .globl s5p_cpu +s5p_cpu: + .long 0 #endif