From patchwork Mon Aug 12 10:02:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 19006 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f198.google.com (mail-vc0-f198.google.com [209.85.220.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 71EA2248EC for ; Mon, 12 Aug 2013 10:02:34 +0000 (UTC) Received: by mail-vc0-f198.google.com with SMTP id ht10sf4386734vcb.1 for ; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=+BeUN+/HpHOUxaqdqfWWJASLR2pEi8q/ybNCbYocD+c=; b=Yc3B74PB7DIxKjPbEkcOJg5oElCfJDLtP8bQhCfp+vxDNVooNmJh3gbFm3qCbpDO4O FhxP3fcaJAdEE8/Skk9k/ybie0qjUhNGt+9C8n+HMNpWDFnaA/5CMhRWGXdMlGvVJLtB 4z/wYLZ9n3keyUe69kTwKWQWimKZm9/Sx7FyU7DqG0OlQMS7wU97XknNxBlX7EvUnz9I I0Ag+YU7nQanLgZJ/s1B5OBjGJT0Shn/hLgM+UeChjv9umSxt1oOzGxu/Vbrt65+BYYW QouhDZWWFVb08t1Ls4QXDKslVOm5qmKgmGNwVn7Fugfo9CJ0exoex7ZFWDNIkTBCgttL VN0g== X-Received: by 10.236.147.50 with SMTP id s38mr10129107yhj.44.1376301754231; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.53.103 with SMTP id a7ls2179864qep.90.gmail; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) X-Received: by 10.52.53.5 with SMTP id x5mr5021908vdo.101.1376301754116; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id aj7si8088932vec.97.2013.08.12.03.02.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:34 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id gd11so2585791vcb.5 for ; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) X-Gm-Message-State: ALoCoQmF8IMUSgZgdFYiCYFXz5lt41lsKDcN4A4TCQg/rVPrYTsX/19Hez8cpNa6vuwJulGUm4S3 X-Received: by 10.52.166.108 with SMTP id zf12mr1260093vdb.106.1376301754028; Mon, 12 Aug 2013 03:02:34 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp86950vcz; Mon, 12 Aug 2013 03:02:33 -0700 (PDT) X-Received: by 10.66.102.1 with SMTP id fk1mr23785399pab.90.1376301753091; Mon, 12 Aug 2013 03:02:33 -0700 (PDT) Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by mx.google.com with ESMTPS id rt3si20868375pbc.143.2013.08.12.03.02.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:33 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.174 is neither permitted nor denied by best guess record for domain of vikas.sajjan@linaro.org) client-ip=209.85.192.174; Received: by mail-pd0-f174.google.com with SMTP id y13so3197599pdi.5 for ; Mon, 12 Aug 2013 03:02:32 -0700 (PDT) X-Received: by 10.67.3.34 with SMTP id bt2mr7275382pad.3.1376301752637; Mon, 12 Aug 2013 03:02:32 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ll5sm38951263pab.19.2013.08.12.03.02.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:31 -0700 (PDT) From: Vikas Sajjan To: mturquette@linaro.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, dianders@chromium.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Date: Mon, 12 Aug 2013 15:32:13 +0530 Message-Id: <1376301734-21847-2-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> References: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vikas.sajjan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds GPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..c400e82 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ + PLL_35XX_RATE(667000000, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ + PLL_35XX_RATE(400000000, 100, 3, 1), + PLL_35XX_RATE(333000000, 222, 4, 2), + PLL_35XX_RATE(200000000, 100, 3, 2), + { }, +}; + static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct device_node *np) fin_pll_rate = _get_rate("fin_pll"); - if (fin_pll_rate == 24 * MHZ) + if (fin_pll_rate == 24 * MHZ) { exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; + } vpllsrc = __clk_lookup("mout_vpllsrc"); if (vpllsrc)