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Wed, 23 Aug 2023 16:47:48 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1%6]) with mapi id 15.20.6699.020; Wed, 23 Aug 2023 16:47:48 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v7 14/24] iommu/msm: Implement an IDENTITY domain Date: Wed, 23 Aug 2023 13:47:28 -0300 Message-ID: <14-v7-de04a3217c48+15055-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v7-de04a3217c48+15055-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: CH2PR14CA0032.namprd14.prod.outlook.com (2603:10b6:610:56::12) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CY5PR12MB6346:EE_ X-MS-Office365-Filtering-Correlation-Id: b787c117-9f88-4f0b-09e7-08dba3f8ab58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RE6UG5K+mBxII4ueiO2HcHjR0MZqHAWpgaxpyQrE4vpaZuguVAkXegfEK0lm0rcMcMwRvDSI6+/DwN6OOfNzYu94v3nJpg2nrlKa6U2tgWU37l5ywKhb1dc+Sk8ucnhzDvpAX10SpbFF/Fkl8vmOvT1T2seUVJ1b0ZxMBmxiZ4fuKOvkiXvEf4Xa3NM/MfYwgRh1CW0kbhcrPQkn6e3TP78TxIvQKLDO3FilOMi6RIVmQAfzlaPKC3zSum2Jrl2nNTuw92/E0GFal6Wn8IDng8ZrL/7S9KpCwGTS/qeNRkZh2WtsDefPlZmE7wYnA/nlXZrOd4fxTPm5IVDBPqyqTNqRwKqKUDFbM9xCIEDEvAxcCDog170mBYrht6dc7uhKuqp17QLd99W7/7sYi7+fjiaf/JM5nKc3Jktxy8bZSy+Qa8W9pFCJF71VhEOPsfwh1mON4ZW2AjHlHLyZ4A22rSlwO/3hjtjF1Wgcg2br2XO2sIsxTwGjJ5sVMgr1yz4PUa6ieLP4cLewKBYDEpQwDMXBNcAOx2c3TbcMgrPWaDJZkUy9MFRrMBQH1OECcldeWNGEsIuqJzjb85o3JuNGT2Pv7NXKkYkDuXxumunqVmjQHug221EpxhhBwSAYMVeGzCZV8KmKKVAMaTr767+MBJV1YrCLBu8si3A13/ehkD7/QzKndE2QBzfPU4u/xpkkKjHxYtO+veJRm8zMBcEoty7MmewCsA6Uolu7dg8gDYxmvpa+idcPjTzeif3pn0Fw1KQ75o6IXe6l6mclza9IlYnUri1McUG3e/UPzllJYnJGp6UsuoTDilvoWzyq1BvyZ1JjGNQlkintlQ53z+dGPH59ql0LIaTxGgJrkVk1dDLsRZKN9/Zps7nIbTKrJehKfmL+pDURt9w/s0fhNuFyrLZNZ9bwadTEyBoR5Zby8OUAfPmOsbrMTjIzSufnJ3UIM5YONRxulBJPk0BEG/u2w2eKICmz/XQ+q9cgxY7t9/szHm0pZHbUeRPrpX0vTSikcWya+NxmMs7j/he+2onGO1cv5Ddrr+nIB/4kU7fPZCpiW8S+LowpywxfJCFnm3tP777SKVutYhvb/YulEi1GRzUPDvLr+TRXvZUu1QjaDFEoVOaClDDioRNEaSmq3A9rq9TqKVvoukageKutKpMsjv6vbcSZG/nxaXhWOpp/nP9TnmbLYEwhMYncRRPJ9/mVG3g7r0TwANQBtbUL3srCC92nNKKzGgegICu7ShKD7qJJH+n9AAw/TJ0UsEVhHGHQ0PZgCV1AKhniUZOEjvX1bHbjzYvUNNjfJQXnX4uPtFz1fFqrI6dCeygCxlvzYB/2/vuw63XRXN2x5pFAO6HCBlujP8+ilsTrs6fcWWQpYXYITJHRLJesAD+J4F+RQsLoktaILrt359WzmRv0GMM75SCBcjO+XNLLDATehhBnUstvqyyFxbMfIYD4s1nK3OoRDN8tppY5+nXkhOvvNV1dA2PWp/YbUQQ+M7HmHTgWYf8I696VSKXmali0CI+zPU/k/olHulTT1sgI4iML1C1lgxQLtR0Xvb3Bb1T4sf4ZWkeeenUAtwphgq29LElJnv8v X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b787c117-9f88-4f0b-09e7-08dba3f8ab58 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2023 16:47:42.8913 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0uCqYQgewyVlzMOrj/UwNb9X6nNkRO2UF+44sw7rw2O+crFplGUPoNQhnYu+SisQ X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6346 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org What msm does during msm_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Reviewed-by: Lu Baolu Signed-off-by: Jason Gunthorpe Reviewed-by: Jerry Snitselaar --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + if (domain == identity_domain || !domain) + return 0; + + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) {