From patchwork Thu Jun 19 08:39:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 32166 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f72.google.com (mail-oa0-f72.google.com [209.85.219.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A5B36206A0 for ; Thu, 19 Jun 2014 08:39:24 +0000 (UTC) Received: by mail-oa0-f72.google.com with SMTP id eb12sf13796321oac.7 for ; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=3ZsQcJnfIdBsumPo7B/tucIqCKlBs7DFNv++cL6Cx3o=; b=hk5FVFc1DQWfpVqKsxi3IzJDFbsMBd1g5jdC2zlEHdTuMdNcMk2k7ewm6D+z0W6T4J stpJlxUBLguVrR6G/3uBjKV/2+6kY0Oe9XjIxxHUNBNXSOL8m3FWp6qE6Z1myhcPaKUc LIDQRFQjicL9eSs/L1TpNHufGUPZ7YhdP/hQtdk/c6X7K2IeXutJoFIna2MkDANKbjpG OBiJiVd4Xzr90FBh0GC6QbrQKCqp4Hktp48GmnJZd6y6RZAT7vN9GsOADfWRTMG1kvoV oiQjyWWJ0RV6+FWTAu7FRUKUHOfp6L5//gc30AUdUNLIMxwfGE/TOlfzP6y/Pl6REA1v xbqw== X-Gm-Message-State: ALoCoQlqwgbBP1jSWbIWmuej4CdEcs5n/CwPxl6CZ0i2fyJswAO0+WvgfnmlmUC01/h+4zhmeFLJ X-Received: by 10.42.12.74 with SMTP id x10mr1523053icx.20.1403167163736; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.95.179 with SMTP id i48ls424807qge.82.gmail; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) X-Received: by 10.52.232.133 with SMTP id to5mr2446672vdc.16.1403167163628; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) Received: from mail-ve0-x22c.google.com (mail-ve0-x22c.google.com [2607:f8b0:400c:c01::22c]) by mx.google.com with ESMTPS id qe9si2045459vcb.79.2014.06.19.01.39.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 19 Jun 2014 01:39:23 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::22c as permitted sender) client-ip=2607:f8b0:400c:c01::22c; Received: by mail-ve0-f172.google.com with SMTP id jz11so1991459veb.17 for ; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) X-Received: by 10.220.92.193 with SMTP id s1mr891103vcm.34.1403167163522; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.54.6 with SMTP id vs6csp346142vcb; Thu, 19 Jun 2014 01:39:23 -0700 (PDT) X-Received: by 10.66.163.164 with SMTP id yj4mr3707505pab.91.1403167162800; Thu, 19 Jun 2014 01:39:22 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id hn3si5090563pac.3.2014.06.19.01.39.22; Thu, 19 Jun 2014 01:39:22 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757589AbaFSIjV (ORCPT + 8 others); Thu, 19 Jun 2014 04:39:21 -0400 Received: from mail-pb0-f53.google.com ([209.85.160.53]:65102 "EHLO mail-pb0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757460AbaFSIjT (ORCPT ); Thu, 19 Jun 2014 04:39:19 -0400 Received: by mail-pb0-f53.google.com with SMTP id uo5so1697986pbc.12 for ; Thu, 19 Jun 2014 01:39:19 -0700 (PDT) X-Received: by 10.68.139.36 with SMTP id qv4mr3940274pbb.82.1403167158954; Thu, 19 Jun 2014 01:39:18 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id ox3sm7309258pbb.88.2014.06.19.01.39.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Jun 2014 01:39:18 -0700 (PDT) From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org, Kukjin Kim , Daniel Lezcano , Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Riley , Doug Anderson , Tomasz Figa Subject: [PATCH v2] clocksource: exynos-mct: Register the timer for stable udelay Date: Thu, 19 Jun 2014 14:09:05 +0530 Message-Id: <1403167145-5267-1-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.9.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Original-Sender: amit.daniel@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::22c as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@ Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch register the exynos mct clocksource as the current timer as it has constant clock rate. This will generate correct udelay for the exynos platform and avoid using unnecessary calibrated jiffies. This change has been tested on exynos5420 based board and udelay is very close to expected. Signed-off-by: Amit Daniel Kachhap --- Changes in V2: * Added #defines for ARM and ARM64 as pointed by Doug Anderson. Patches from David Riley confirmed that udelay is broken in exynos5420. Link to those patches are, 1) https://patchwork.kernel.org/patch/4344911/ 2) https://patchwork.kernel.org/patch/4344881/ drivers/clocksource/exynos_mct.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index f71d55f..02927e2 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -195,10 +195,25 @@ static u64 notrace exynos4_read_sched_clock(void) return exynos4_frc_read(&mct_frc); } +static struct delay_timer exynos4_delay_timer; + +static unsigned long exynos4_read_current_timer(void) +{ +#ifdef ARM + return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); +#else /* ARM64, etc */ + return exynos4_frc_read(&mct_frc); +#endif +} + static void __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(); + exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; + exynos4_delay_timer.freq = clk_rate; + register_current_timer_delay(&exynos4_delay_timer); + if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name);