From patchwork Wed Dec 16 12:21:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 58502 Delivered-To: patch@linaro.org Received: by 10.112.89.199 with SMTP id bq7csp665887lbb; Wed, 16 Dec 2015 04:22:31 -0800 (PST) X-Received: by 10.66.140.39 with SMTP id rd7mr62456056pab.86.1450268540435; Wed, 16 Dec 2015 04:22:20 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w3si5101455pfa.214.2015.12.16.04.22.20; Wed, 16 Dec 2015 04:22:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933730AbbLPMWT (ORCPT + 4 others); Wed, 16 Dec 2015 07:22:19 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:12880 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932551AbbLPMWR (ORCPT ); Wed, 16 Dec 2015 07:22:17 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZG00HPKAD3WA80@mailout2.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 16 Dec 2015 12:22:15 +0000 (GMT) X-AuditID: cbfec7f4-f79026d00000418a-3f-56715776567d Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 71.19.16778.67751765; Wed, 16 Dec 2015 12:22:14 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZG0012YACWHH70@eusync4.samsung.com>; Wed, 16 Dec 2015 12:22:14 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Joonyoung Shim , Seung-Woo Kim , Andrzej Hajda , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Tobias Jakobi , Gustavo Padovan Subject: [PATCH v3 5/7] drm/exynos: mixer: refactor layer setup Date: Wed, 16 Dec 2015 13:21:46 +0100 Message-id: <1450268508-15028-6-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1450268508-15028-1-git-send-email-m.szyprowski@samsung.com> References: <1450268508-15028-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOLMWRmVeSWpSXmKPExsVy+t/xa7pl4YVhBl/uGVjcWneO1WLjjPWs Fle+vmez2PlgF7vFpPsTWCxe3LvIYvH6haHFjPP7mCzWHrnLbjFj8ks2i7bVH1gduD3udx9n 8vh3jN1j56S9TB59W1YxenzeJBfAGsVlk5Kak1mWWqRvl8CVsXTxdbaC87IV1w/MY29g/CjR xcjJISFgIjH12SYmCFtM4sK99WxdjFwcQgJLGSXO3PjNAuE0MUmsejuLBaSKTcBQouttFxuI LSLgJtF0eCYrSBGzQB+zRFPzQ7CEsIC9xJdt28FsFgFViRmbusBW8Ap4SFyc/o4NYp2cxP+X K8DinAKeEmuPz2QHsYWAah6s3sE8gZF3ASPDKkbR1NLkguKk9FxDveLE3OLSvHS95PzcTYyQ 4Puyg3HxMatDjAIcjEo8vBciC8KEWBPLiitzDzFKcDArifA+lCsME+JNSaysSi3Kjy8qzUkt PsQozcGiJM47d9f7ECGB9MSS1OzU1ILUIpgsEwenVAOjoy8707bX6zPU+TKZvt7sWVzZ92lS l7DfIufXpz+HqTzvP/GDZ9Ohzh3yLdM0ViprKM5qENJ90mW4z+ZbzGJT37V7Q5aGPpHV5d8Q Nuev4px1DlvdvzjI6Mx/JGy00brmlWXumzMLAzZXtBb0JyyUn2RvzDz9T7WdyWGvSw9Wt95w cFxeuqdfiaU4I9FQi7moOBEApCQEXzoCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Properly configure blending properties of given hardware layer based on the selected pixel format. Currently only per-pixel-based alpha is possible when respective pixel format has been selected. Configuration of global, per-plane alpha value, color key and background color will be added later. This patch is heavily inspired by earlier work done by Tobias Jakobi . Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_mixer.c | 43 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/exynos/regs-mixer.h | 1 + 2 files changed, 44 insertions(+) -- 1.9.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index c572e271579e..ae7b122274ac 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -165,6 +165,16 @@ static const u8 filter_cr_horiz_tap4[] = { 70, 59, 48, 37, 27, 19, 11, 5, }; +static inline bool is_alpha_format(unsigned int pixel_format) +{ + switch (pixel_format) { + case DRM_FORMAT_ARGB8888: + return true; + default: + return false; + } +} + static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) { return readl(res->vp_regs + reg_id); @@ -294,6 +304,37 @@ static void vp_default_filter(struct mixer_resources *res) filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); } +static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, + bool alpha) +{ + struct mixer_resources *res = &ctx->mixer_res; + u32 val; + + val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ + if (alpha) { + /* blending based on pixel alpha */ + val |= MXR_GRP_CFG_BLEND_PRE_MUL; + val |= MXR_GRP_CFG_PIXEL_BLEND_EN; + } + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), + val, MXR_GRP_CFG_MISC_MASK); +} + +static void mixer_cfg_vp_blend(struct mixer_context *ctx) +{ + struct mixer_resources *res = &ctx->mixer_res; + u32 val; + + /* + * No blending at the moment since the NV12/NV21 pixelformats don't + * have an alpha channel. However the mixer supports a global alpha + * value for a layer. Once this functionality is exposed, we can + * support blending of the video layer through this. + */ + val = 0; + mixer_reg_write(res, MXR_VIDEO_CFG, val); +} + static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) { struct mixer_resources *res = &ctx->mixer_res; @@ -519,6 +560,7 @@ static void vp_video_buffer(struct mixer_context *ctx, mixer_cfg_scan(ctx, mode->vdisplay); mixer_cfg_rgb_fmt(ctx, mode->vdisplay); mixer_cfg_layer(ctx, plane->index, state->zpos + 1, true); + mixer_cfg_vp_blend(ctx); mixer_run(ctx); mixer_vsync_set_update(ctx, true); @@ -634,6 +676,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, mixer_cfg_scan(ctx, mode->vdisplay); mixer_cfg_rgb_fmt(ctx, mode->vdisplay); mixer_cfg_layer(ctx, win, state->zpos + 1, true); + mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->pixel_format)); /* layer update mandatory for mixer 16.0.33.0 */ if (ctx->mxr_ver == MXR_VER_16_0_33_0 || diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index dbdbc0af3358..7f22df5bf707 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -113,6 +113,7 @@ #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) +#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20)) #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)