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Thu, 20 Apr 2017 14:16:46 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Stephen Boyd , Michael Turquette , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 2/4] clk: samsung: exynos-audss: Convert to the new clk_hw API Date: Thu, 20 Apr 2017 15:16:37 +0200 Message-id: <1492694199-9553-3-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1492694199-9553-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrIIsWRmVeSWpSXmKPExsWy7djPc7r7t/yIMDi4g8Ni44z1rBbXvzxn tTh/fgO7xceee6wWM87vY7JYe+Quu8XFU64Wh9+0s1r8ONPN4sDp8f5GK7vH5b5eJo9NqzrZ PPq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSvjyYU/rAW3DCoWHL/K3MB4QKOLkZNDQsBEYubz XUwQtpjEhXvr2boYuTiEBJYySvxYs5EJwvnMKLH323nWLkYOsI6z37Ug4ssYJQ5e+A5V1MAk 8ffvX7BRbAKGEl1vu9hAbBEBB4nPn14zghQxC+xkkpjwcyVYQlggQGLiz5lgDSwCqhJPXx5l BLF5Bdwl+rZ8ZIW4SU7i5LHJYDangIfE1El32EEGSQg0s0ts27SNHeIkWYlNB5gh6l0kOnYv YYSwhSVeHd/CDmHLSFye3M0CYfczSjS1akPYMxglzr3lhbCtJQ4fvwi2i1mAT2LStunMEON5 JTrahCBKPCTO/vvHBmE7Shw8+AxslZDAbEaJ3pP5ExhlFjAyrGIUSS0tzk1PLTbVK07MLS7N S9dLzs/dxAiM6NP/jn/dwbj0mNUhRgEORiUeXoU1PyKEWBPLiitzDzFKcDArifD6bgIK8aYk VlalFuXHF5XmpBYfYpTmYFES5+U6dS1CSCA9sSQ1OzW1ILUIJsvEwSnVwKhemHd3he/EC0fO lwSpXAtc0Nm08tFvabmMmqsOpb8y4m4zvFPQOKkpxjvlw5xWnhf/Xgm8fFH3hPNkhuj1Rw1H 2QUCw/7tyZ858aG/8I0//5PLf8RKZB/p+ic4c3OUxuccvv9131drRYs+XPQ5KTDmS7pTt7bP iqADR3wiJBYkLDK4uGWyPK8SS3FGoqEWc1FxIgD2Zzfr5AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsVy+t/xy7rXt/yIMNh1mcti44z1rBbXvzxn tTh/fgO7xceee6wWM87vY7JYe+Quu8XFU64Wh9+0s1r8ONPN4sDp8f5GK7vH5b5eJo9NqzrZ PPq2rGL0+LxJLoA1ys0mIzUxJbVIITUvOT8lMy/dVik0xE3XQkkhLzE31VYpQtc3JEhJoSwx pxTIMzJAAw7OAe7BSvp2CW4ZTy78YS24ZVCx4PhV5gbGAxpdjBwcEgImEme/a3UxcgKZYhIX 7q1n62Lk4hASWMIoMb3rCDtIQkigiUniyVoFEJtNwFCi620XG4gtIuAg8fnTa0aQBmaB3UwS F08+ZgRJCAv4Sax7850FxGYRUJV4+vIoWJxXwF2ib8tHVohtchInj00GszkFPCSmTroDtcxd 4tS2VawTGHkXMDKsYhRJLS3OTc8tNtIrTswtLs1L10vOz93ECAzubcd+btnB2PUu+BCjAAej Eg/viZU/IoRYE8uKK3MPMUpwMCuJ8PpuAgrxpiRWVqUW5ccXleakFh9iNAU6aiKzlGhyPjDy 8kriDU0MzS0NjYwtLMyNjJTEead+uBIuJJCeWJKanZpakFoE08fEwSnVwFj0Z+ssXTvFrrKX P3rZ5h97ZT5NfcYKEXN12YU6/Fv0BETX/pgi0Bl9acsfiYKZi3sNlwkkefln5zGm9S0QLbKf VVLffmux/41pwe989y50cpt4psEkdpXvbfkeR+6Js3mWJbOtm6a6ZOpq+zvNT/kaH5W9Mvpw U+s5Q8f/2T/aIxR63L72KCmxFGckGmoxFxUnAgDlqojKhAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170420131646eucas1p1d302e43fd2823f8e8defe93a24e03e29 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170420131646eucas1p1d302e43fd2823f8e8defe93a24e03e29 X-RootMTR: 20170420131646eucas1p1d302e43fd2823f8e8defe93a24e03e29 References: <1492694199-9553-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Clock providers should use the new struct clk_hw based API, so convert Exynos Audio Subsystem clock provider to the new approach. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos-audss.c | 55 +++++++++++++++++----------------- 1 file changed, 28 insertions(+), 27 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index cb7df358a27d..e8f89529da07 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -22,9 +22,8 @@ #include static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; static void __iomem *reg_base; -static struct clk_onecell_data clk_data; +static struct clk_hw_onecell_data *clk_data; /* * On Exynos5420 this will be a clock which has to be enabled before any * access to audss registers. Typically a child of EPLL. @@ -110,18 +109,18 @@ static void exynos_audss_clk_teardown(void) int i; for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_mux(clk_table[i]); + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_mux(clk_data->hws[i]); } for (; i < EXYNOS_SRP_CLK; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_divider(clk_table[i]); + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_divider(clk_data->hws[i]); } - for (; i < clk_data.clk_num; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_gate(clk_table[i]); + for (; i < clk_data->num; i++) { + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_gate(clk_data->hws[i]); } } @@ -133,6 +132,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *sclk_pcm_p = "sclk_pcm0"; struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct exynos_audss_clk_drvdata *variant; + struct clk_hw **clk_table; struct resource *res; int i, ret = 0; @@ -149,14 +149,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) epll = ERR_PTR(-ENODEV); - clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + clk_data = devm_kzalloc(&pdev->dev, + sizeof(*clk_data) + + sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); - if (!clk_table) + if (!clk_data) return -ENOMEM; - clk_data.clks = clk_table; - clk_data.clk_num = variant->num_clks; + clk_data->num = variant->num_clks; + clk_table = clk_data->hws; pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); pll_in = devm_clk_get(&pdev->dev, "pll_in"); @@ -176,7 +177,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } } } - clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", + clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); @@ -187,53 +188,53 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) mout_i2s_p[2] = __clk_get_name(sclk_audio); - clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", + clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); - clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", + clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); - clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL, + clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, "dout_aud_bus", "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); - clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", + clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s", "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); - clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", + clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 0, 0, &lock); - clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", + clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 2, 0, &lock); - clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", + clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 3, 0, &lock); - clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", + clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); - clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", + clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm", sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); if (variant->has_adma_clk) { - clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 9, 0, &lock); } - for (i = 0; i < clk_data.clk_num; i++) { + for (i = 0; i < clk_data->num; i++) { if (IS_ERR(clk_table[i])) { dev_err(&pdev->dev, "failed to register clock %d\n", i); ret = PTR_ERR(clk_table[i]); @@ -241,7 +242,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } } - ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, &clk_data); if (ret) { dev_err(&pdev->dev, "failed to add clock provider\n");