From patchwork Wed Jun 14 15:33:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105543 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380577obh; Wed, 14 Jun 2017 08:12:14 -0700 (PDT) X-Received: by 10.84.129.65 with SMTP id 59mr644406plb.166.1497453134250; Wed, 14 Jun 2017 08:12:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453134; cv=none; d=google.com; s=arc-20160816; b=yBUmWuyRa2oCBUnlOHlXd+uZoblyo4n8ouWhNiy4Vf/8sMu7t4S1S1hz7kDzsXOSNk ZqWW9p0tgXWvZMHSoSnMwqZsakSW/B1pICXVKUen3Hkepms0LmWMrjv4HuZAFtdad6GB n+zRhJazPOt9LMWm4+k6t03LpBc2MxUiQ4eX/1qf9ljt4MT79eJZWVwNLk7agsFO6UQM SQ+awf5TSUbvThtxDGjmzfhI+farT/QRU9UPRUMOZsCPN6PmBIKV/aYAcNy8k6lTfhFc ATwGyXniVqhFb1reosh9y4wQ1YFThuINL7Pzsy8wovillU63CdcFkPp1Yi0tanRtwtAW YIDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=+mAcA1kZHZ9TtF8TCI8mPyDAmOSGjMZEi3/9QxPaV1M=; b=KCqw6Gvl6U8fUiKuLsvzFbp0qH+QikbITQaMaLTvd76u2vT7zT8E1qDR4wCmxYlaeo YDjtzmm+XDlqyHx4wbq1YpDlsjT5zbKSLCb78EI7Mhm2J2eMHkg81zcfwF9KjdJ/+fGC U0pix7q3Wk+uOHpDVf3hT8BJM369WHSX/WwPcPx3TvVLqA16szHfHYO1VDeZNbW3k9Xu YiJTSYyZuFYdKY/p/w33ZYNfBlmTVqCaLnGzxh37TuCbJI6Z386BrUrbhAbEcbje09zU NpBTA84C9phYGXq+s/JxjPHusLcz95dfbIgle5c9OFaWrx1GK5+rht5lZc5eESmtJ0xQ z6wQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v30si168561pfl.262.2017.06.14.08.12.14; Wed, 14 Jun 2017 08:12:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752656AbdFNPMH (ORCPT + 1 other); Wed, 14 Jun 2017 11:12:07 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7848 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752519AbdFNPEM (ORCPT ); Wed, 14 Jun 2017 11:04:12 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60184; Wed, 14 Jun 2017 23:03:26 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:12 +0800 From: John Garry To: , CC: , , , , , "John Garry" Subject: [PATCH v6 00/22] hisi_sas: hip08 support Date: Wed, 14 Jun 2017 23:33:10 +0800 Message-ID: <1497454412-91194-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503E.0145, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: dc8dbd61024a28b1df27b33c33fa6a83 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org This patchset adds support for the HiSilicon SAS controller in the hip08 chipset. The key difference compared to earlier chipsets is that the controller is an integrated PCI endpoint in hip08. As such, the controller is a pci device (not a platform device, like v2 hw in hip07). The driver is refactored so it can support both platform and pci device-based controllers. New hw layer file hisi_sas_v3_hw.c is added for v3 hw support, which also includes pci device proving and initialisation. Common functionality is still in hisi_sas_main.c, along with platform device probing and initialization. As for the patches, (ignoring #1-3) the first few reorganise some functions from v2 hw.c into main.c, as they are required for v3 hw. Then support is added for pci device-based controller in subsequent patches. And then hip08 support is added in the final patches. Differences to v5 series: - Fixed erroneous spinlock flag reuse - Omit support ECC and AXI bus fatal error support Difference to v4 series: -report SAS_DATA_UNDERRUN to libsas for underflow Differences to v3 series: - Addressed Christoph's comments, including: - remove msi disable in probe, and improve irq registration and deregistration - remove hisi_sas_is_rw_cmd() to check underflow, and use scsi_cmnd underflow field instead Differences to v2 series: - Add patch to change hisi_sas_device.device_id size - Add device dq pointer - Remove hisi_sas_v3_hw prototype in v3 driver - Add explicit comment in hisi_sas_get_fw_info() Differences to v1 series: - Addressed Arnd's comments, including: - read sas address from device node DSD under PCI host bridge - add comment in fatal axi error patch commit log regarding controller reset - eliminate hisi_sas_pci_init.c, and move functionality into hisi_sas_v3_hw.c, eliminating one layer of indirection John Garry (5): scsi: hisi_sas: define hisi_sas_device.device_id as int scsi: hisi_sas: add pci_dev in hisi_hba struct scsi: hisi_sas: create hisi_sas_get_fw_info() scsi: hisi_sas: add skeleton v3 hw driver scsi: hisi_sas: add initialisation for v3 pci-based controller Xiang Chen (17): scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() scsi: hisi_sas: optimise the usage of hisi_hba.lock scsi: hisi_sas: relocate get_ata_protocol() scsi: hisi_sas: relocate sata_done_v2_hw() scsi: hisi_sas: relocate get_ncq_tag_v2_hw() scsi: hisi_sas: add v3 hw init scsi: hisi_sas: add v3 hw PHY init scsi: hisi_sas: add phy up/down/bcast and channel ISR scsi: hisi_sas: add v3 cq interrupt handler scsi: hisi_sas: add v3 code to send SSP frame scsi: hisi_sas: add v3 code to send SMP frame scsi: hisi_sas: add v3 code to send ATA frame scsi: hisi_sas: add v3 code for itct setup and free scsi: hisi_sas: add v3 code to send internal abort command scsi: hisi_sas: add get_wideport_bitmap_v3_hw() scsi: hisi_sas: add v3 code to fill some more hw function pointers scsi: hisi_sas: modify internal abort dev flow for v3 hw drivers/scsi/hisi_sas/Kconfig | 10 +- drivers/scsi/hisi_sas/Makefile | 1 + drivers/scsi/hisi_sas/hisi_sas.h | 42 +- drivers/scsi/hisi_sas/hisi_sas_main.c | 363 +++++-- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 51 +- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 179 +--- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 1846 ++++++++++++++++++++++++++++++++ 7 files changed, 2225 insertions(+), 267 deletions(-) create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c -- 1.9.1