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J . Bottomley" , "Martin K . Petersen" Cc: Alim Akhtar , Avri Altman , Bart Van Assche , Minwoo Im , gost.dev@samsung.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, Jeuk Kim Subject: [PATCH 2/3] ufs: pci: Add support MCQ for QEMU-based UFS Date: Fri, 31 May 2024 19:38:20 +0900 Message-Id: <20240531103821.1583934-3-minwoo.im@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240531103821.1583934-1-minwoo.im@samsung.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIJsWRmVeSWpSXmKPExsWy7bCmma7P6sg0g61XpCwezNvGZvHy51U2 i2kffjJb3Dywk8liYz+Hxf2t1xgtLu+aw2bRfX0Hm8Xy4/+YLJ6dPsDswOVx+Yq3x7RJp9g8 Pj69xeLRt2UVo8fnTXIe7Qe6mQLYorJtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0t zJUU8hJzU22VXHwCdN0yc4AOU1IoS8wpBQoFJBYXK+nb2RTll5akKmTkF5fYKqUWpOQUmBfo FSfmFpfmpevlpZZYGRoYGJkCFSZkZzTsv81U8EK8Yu6cTtYGxi/CXYycHBICJhI3jnxi62Lk 4hAS2MMocWpWByOE84lRYtGmv8wQzjdGiROLnzDDtExqOcwEkdjLKLH67HwWCOc3o8Txt3sZ QarYBNQlGqa+YgGxRQSqJTa3/wVbwizQxyTRPns+axcjB4ewgKPE9dWGIDUsAqoS908tAuvl FbCRuHxyGRPENnmJ/QfPgm3mFLCVaPl/kg2iRlDi5MwnYPOZgWqat84GO1VCoJFD4s/7aYwQ zS4St46fZYewhSVeHd8CZUtJvOxvg7LLJX6+mQRVXyFxcNZtNpDbJATsJa49TwExmQU0Jdbv 0oeIKkscuQW1lU+i4/Bfdogwr0RHmxDEDGWJj4cOQYNKUmL5pddsELaHxLPPa6GBO4FR4tP2 XWwTGBVmIXlmFpJnZiEsXsDIvIpRKrWgODc9NdmowFA3L7UcHsnJ+bmbGMFpVct3B+Pr9X/1 DjEycTAeYpTgYFYS4f2VHpEmxJuSWFmVWpQfX1Sak1p8iNEUGNwTmaVEk/OBiT2vJN7QxNLA xMzM0NzI1MBcSZz3XuvcFCGB9MSS1OzU1ILUIpg+Jg5OqQambkO/lBmG5k9fL45ObZnwrPXv 7Sxv6fvybHnKlTwrb7/ZHfPQ0Uc6e4Pbb8t4L8153/99ntDwKcnSeb0jl2/f2jhfnhW3Q9T5 TntJTlu7/rfkWl/lludS9SVFZyzPblm5RfUYhzy3plvWH1tL2V2cbMqrIrNuS+kcn/Hv6SLp 45ueXOVZ8FPSeNmnb5O3Cf/gy5HRS/3uOXXSk27lltSHjgZzfjnoP791e56aiBbH4Q9HOi7v z1nRm2nL9Unu+h5DpYkPk85LteyM5Pq78OOCJXkLYp7rXD/2463WtuWWz6ZcCvgo0Xaq8VTu lP2NCZIGa0wMRD67ZO/JtuWNjXJ54z9Le9n/12/LGf7me/YVK7EUZyQaajEXFScCALMQ6w40 BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWy7bCSnK736sg0gwVbLCwezNvGZvHy51U2 i2kffjJb3Dywk8liYz+Hxf2t1xgtLu+aw2bRfX0Hm8Xy4/+YLJ6dPsDswOVx+Yq3x7RJp9g8 Pj69xeLRt2UVo8fnTXIe7Qe6mQLYorhsUlJzMstSi/TtErgyGvbfZip4IV4xd04nawPjF+Eu Rk4OCQETiUkth5m6GLk4hAR2M0q8aX3EApGQlNh3+iYrhC0scb/lCCtE0U9GiY1b+sGK2ATU JRqmvgKzRQSqJTa3/2UDKWIWmMYksWgWSDcHh7CAo8T11YYgNSwCqhL3Ty1iBLF5BWwkLp9c xgSxQF5i/8GzzCA2p4CtRMv/k2wgthBQzerLL1kg6gUlTs58AmYzA9U3b53NPIFRYBaS1Cwk qQWMTKsYJVMLinPTc5MNCwzzUsv1ihNzi0vz0vWS83M3MYJDX0tjB+O9+f/0DjEycTAeYpTg YFYS4f2VHpEmxJuSWFmVWpQfX1Sak1p8iFGag0VJnNdwxuwUIYH0xJLU7NTUgtQimCwTB6dU A9P5Jae2/80WWjdd7Ilj+aZUc6a/TEaSoZZNZgKTgreefbjwO9vagBtGL5JW1M4pm/vqe1L8 yuT7Lxbd2GJebXc1MI0hUqc7wfbsvWdRW10q+Cz6bp5RlWLZve58ksOykuOz018aFOX9tth0 p1+mpKraZFJt9f/n3nuPiVbqriz4Uic4w3MN6/3FnDxR4bfMNzDFV0Ve1jWT7c+ZWHExy9Rf Z4+r9KT9PzwWzHIOVbO8zZne4JpTZX1EeHpE6LNnr1NnfJJ5I6F/cM7f+0GTf29a4yW9oMz9 qcTZC4KZKyuOt3keUbDO8qpX6F1yd21F3Y83GuFWUdskd1tVuqpObulJienymqipHcCrWC8T rcRSnJFoqMVcVJwIAHm00EfsAgAA X-CMS-MailID: 20240531104947epcas2p30506632eb56025711dfb5768e2f77154 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240531104947epcas2p30506632eb56025711dfb5768e2f77154 References: <20240531103821.1583934-1-minwoo.im@samsung.com> Recently, ufs-mcq feature has been introduced to QEMU hw/ufs device [1]. This patch adds MCQ support for upstream QEMU UFS PCI controller. This patch provides mandatory vops callbacks to make UFS controller work properly on MCQ mode. Operation and Runtime Config register stride is fixed to 48bytes which is implemented by qemu. [1] https://lore.kernel.org/qemu-devel/cover.1716876237.git.jeuk20.kim@samsung.com/ Signed-off-by: Minwoo Im --- drivers/ufs/host/ufshcd-pci.c | 48 ++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c index 0aca666d2199..d4d64a29390e 100644 --- a/drivers/ufs/host/ufshcd-pci.c +++ b/drivers/ufs/host/ufshcd-pci.c @@ -20,6 +20,8 @@ #include #include +#define MAX_SUPP_MAC 64 + struct ufs_host { void (*late_init)(struct ufs_hba *hba); }; @@ -446,6 +448,49 @@ static int ufs_intel_mtl_init(struct ufs_hba *hba) return ufs_intel_common_init(hba); } +static int ufs_redhat_get_hba_mac(struct ufs_hba *hba) +{ + return MAX_SUPP_MAC; +} + +static int ufs_redhat_mcq_config_resource(struct ufs_hba *hba) +{ + hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba); + + return 0; +} + +static int ufs_redhat_op_runtime_config(struct ufs_hba *hba) +{ + struct ufshcd_mcq_opr_info_t *opr; + int i; + + u32 sqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQDAO, 0)); + u32 sqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQISAO, 0)); + u32 cqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQDAO, 0)); + u32 cqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQISAO, 0)); + + hba->mcq_opr[OPR_SQD].offset = sqdao; + hba->mcq_opr[OPR_SQIS].offset = sqisao; + hba->mcq_opr[OPR_CQD].offset = cqdao; + hba->mcq_opr[OPR_CQIS].offset = cqisao; + + for (i = 0; i < OPR_MAX; i++) { + opr = &hba->mcq_opr[i]; + opr->stride = 48; + opr->base = hba->mmio_base + opr->offset; + } + + return 0; +} + +static struct ufs_hba_variant_ops ufs_redhat_hba_vops = { + .name = "redhat-pci", + .get_hba_mac = ufs_redhat_get_hba_mac, + .mcq_config_resource = ufs_redhat_mcq_config_resource, + .op_runtime_config = ufs_redhat_op_runtime_config, +}; + static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = { .name = "intel-pci", .init = ufs_intel_common_init, @@ -591,7 +636,8 @@ static const struct dev_pm_ops ufshcd_pci_pm_ops = { }; static const struct pci_device_id ufshcd_pci_tbl[] = { - { PCI_VENDOR_ID_REDHAT, 0x0013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_REDHAT, 0x0013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, + (kernel_ulong_t)&ufs_redhat_hba_vops }, { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },