[v2,0/2] add NXP LINFlexD UART clock support for S32G2/S32G3

Message ID	20241014144501.388050-1-ciprianmarian.costea@oss.nxp.com
Headers	show Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2076.outbound.protection.outlook.com [40.107.20.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9D237C6E6; Mon, 14 Oct 2024 14:45:09 +0000 (UTC) From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Chester Lin <chester62515@gmail.com> Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, NXP S32 Linux Team <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>, Alberto Ruiz <aruizrui@redhat.com>, Enric Balletbo <eballetb@redhat.com>, Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Subject: [PATCH v2 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 Date: Mon, 14 Oct 2024 17:44:59 +0300 Message-ID: <20241014144501.388050-1-ciprianmarian.costea@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1
Series	add NXP LINFlexD UART clock support for S32G2/S32G3 \| expand [v2,0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 [v2,1/2] dt-bindings: linflexuart: add clock definitions [v2,2/2] serial: fsl_linflexuart: add clock support

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20241014144501.388050-1-ciprianmarian.costea@oss.nxp.com

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From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Chester Lin <chester62515@gmail.com>
Cc: linux-kernel@vger.kernel.org,
	linux-serial@vger.kernel.org,
	devicetree@vger.kernel.org,
	NXP S32 Linux Team <s32@nxp.com>,
	Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	Enric Balletbo <eballetb@redhat.com>,
	Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Subject: [PATCH v2 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3
Date: Mon, 14 Oct 2024 17:44:59 +0300
Message-ID: <20241014144501.388050-1-ciprianmarian.costea@oss.nxp.com>
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	=?utf-8?q?NmS3qOoSug5rimrd/DefXpzQkDPwyB18MoRRdUse6D4PjTnMIvMlEi3Osp8xjb0Z8?=
	=?utf-8?q?cOYEJMBFA6rcQ3wAh5/tmyO3MxlWtKjacLDlnjpAu61aFSeu8ex3W3mNHapj7ZB18?=
	=?utf-8?q?z6O6844eJ06uf3DP2USKNswXiq47zjaBgclkDdIdPf+Ka9q9xGW+lLtJ8IbUkwUsA?=
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	=?utf-8?q?OCgXXFON9PIZRb1iKTAFji15xEF4bWjr8uHDLTeqfKdsttZ7ClZayLlMQNKwU3HfD?=
	=?utf-8?q?7cyyJMg8Fr9M5pagnIXolQxxgr3u8Ydg+RBLDs4QDoncyfVSVIcx9GTpKW7JL1AOa?=
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	=?utf-8?q?oWu11RZuzY/qBSm66aJJNjyNlR0pKemzISo6Y25JGWl/AGREHcO6UH4G00tbClaUm?=
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	=?utf-8?q?rXNVQzpaL0JUHEW5fjpt4NkpQDy81b+FvgQpDABHuc9TW67qPGfti+SQdScEXqlmO?=
	=?utf-8?q?2m55mNomzMElBjbvbzihDYMhYSbMGxblYF6XuoZWOBAzYYbGOQdC282Ajfvjoq0C+?=
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	=?utf-8?q?M1+3Ioz0dEWHTW4vMPbcdY8acGp1muR2BxSF5YMlgrXGY014oxsPA1BFPwf5aRNbt?=
	=?utf-8?q?lImC4Uhf4Jvmi9laiQbzvv+xsZXfnyWbiEx7CBaPonOukrycUs4TYNAq+GMMecbba?=
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	=?utf-8?q?t9/AZgqhROIkpkl0ZzQk+eGq7qLDfJXDx5sgvub5Uw9OedQj2ES0pxPyvp/Qaf8CG?=
	=?utf-8?q?pv4n13W58Ry3JZTVK5vjgCgjVB7nFdZLyqjV+pB9mDBDTK3WtxNG/Kybi1cHM0JGa?=
	=?utf-8?q?pRmyKOHl4suWzx18rEogODWAo1No8L2/dy3mZhKM7rqkgggCHK2aCkIlsedzu4wPX?=
	=?utf-8?q?/H2fDTeEth+boz38+3m63aEuy3ko7Ic0OhHnTHUfSD2pq0nVX1bTJNtRMmJD9Yjh5?=
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	=?utf-8?q?Gsxmsu18pl/7cGAgtkFB4Mo/uaXf3nB1lK2VzhGNKNj0buIZmfMaYqwkMNwP0StgN?=
	=?utf-8?q?BoVSNtRPhTggJHmq7ZjsdiMuSBypLvAfjlOpQeg7j0fiWe1vf26ob+4HVeAhSIlt1?=
	=?utf-8?q?MFKTd8XNvUj/BRYs06d9bQ/VOmnMFNOBOe9yfDmU+h65TKb4TsCFLKPjdhx5pl2IY?=
	=?utf-8?q?gGeagHdVwvFE5Sadf1eLym+1Bs4hfzUHx9Xlg1sg6dpB3OYUW5x5hlBPKhiK0o/jF?=
	=?utf-8?q?sCFaAET56oZs/Kz8gFzabje9Us/7uPRI0u+Uh74syzMyskoqEZnoxyeHuaqp8m4sR?=
	=?utf-8?q?u9IQPFGYZbXZHDzZyc1uJiwlzOKvBsrYifHw+/Yb5HX/LFaSeGzN1ybdjh+c1Jp4l?=
	=?utf-8?q?pSMVTilIe7upSIpP5gn4NIdaOr5fwS+YlmH3LIVTxfEeTyvberKMZSyY+shhUHAlO?=
	=?utf-8?q?Gq2xr+vyY9/Zu2AaFweL82eK61eGADWcQw=3D=3D?=
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Series

add NXP LINFlexD UART clock support for S32G2/S32G3 | expand

Message

Ciprian Costea Oct. 14, 2024, 2:44 p.m. UTC

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

LINFlexD UART driver is used by S32 SoC family.
Add clocking support as optional in order to not break
existing support for S32V234 SoC.

A separate patch adding clock definitions to
the S32G2/S32G3 based boards devicetree will be sent
for review.

Changes in V2:
- Updated bindings by adding more information related to
required LINFlexD clocks

Ciprian Marian Costea (2):
  dt-bindings: linflexuart: add clock definitions
  serial: fsl_linflexuart: add clock support

 .../bindings/serial/fsl,s32-linflexuart.yaml  | 27 ++++++++
 drivers/tty/serial/fsl_linflexuart.c          | 67 ++++++++++++++-----
 2 files changed, 78 insertions(+), 16 deletions(-)