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[03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series

Message ID 20220127151647.2375449-4-icenowy@nucleisys.com
State New
Headers show
Series Initial support for Nuclei DemoSoC w/ UX600 | expand

Commit Message

Icenowy Zheng Jan. 27, 2022, 3:16 p.m. UTC
Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux.

Add compatible strings for these CPU cores.

Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Rob Herring (Arm) Feb. 9, 2022, 4:05 a.m. UTC | #1
On Thu, 27 Jan 2022 23:16:38 +0800, Icenowy Zheng wrote:
> Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux.
> 
> Add compatible strings for these CPU cores.
> 
> Signed-off-by: Icenowy Zheng <icenowy@nucleisys.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index aa5fb64d57eb..f50f5c3dcc06 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,13 @@  properties:
               - sifive,u54-mc
           - const: sifive,rocket0
           - const: riscv
+      - items:
+          - enum:
+              - nuclei,ux605
+              - nuclei,ux607
+              - nuclei,ux608
+          - const: nuclei,ux600
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set