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[v3,0/3] DW apb_ssi V4 support for Kendryte K210 RISC-V SoC

Message ID 20201206011817.11700-1-damien.lemoal@wdc.com
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Series DW apb_ssi V4 support for Kendryte K210 RISC-V SoC | expand

Message

Damien Le Moal Dec. 6, 2020, 1:18 a.m. UTC 
The Canaan Kendryte K210 RISC-V SoC includes a DesignWare apb_ssi V4
SPI controller implemented with a maximum data frame size of 32-bits
(SSI_MAX_XFER_SIZE=32 synthesis parameter).

This series of patches adds support for this SoC by implementing support
for the 32-bits xfer size configuration. This is done in patch 2.

Patch 3 introduces a workaround for a HW bug on this SoC which triggers
RX FIFO overrun errors when the RX FIFO fills up to its maximum detected
depth of 32. The patch manually reduces the fifo depth to 31.

The first patch documents the new compatible string "canaan,k210-spi"
used to identify this SoC.

Changes from v2:
* Moved DT bindings update patch first in the series
* Tweaked comments for the DFS32 detection code as suggested by Serge
* Added Serge's Acked-by tag to patch 2.

Changes from v1:
* Fixed patch 1 as suggested by Serge: change capability flag name to
  DW_SPI_CAP_DFS32 and fixed the capability detection to use the regular
  position of the dfs filed rather than the new position with DFS32.
  Also enable DW_SPI_CAP_DFS32 for SPI slaves.
* Added Serge's Acked-by tag to patch 2 and 3.

Damien Le Moal (3):
  dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller
  spi: dw: Add support for 32-bits max xfer size
  spi: dw: Add support for the Canaan K210 SoC SPI

 .../bindings/spi/snps,dw-apb-ssi.yaml         |  2 +
 drivers/spi/spi-dw-core.c                     | 44 ++++++++++++++++---
 drivers/spi/spi-dw-mmio.c                     | 16 +++++++
 drivers/spi/spi-dw.h                          |  5 +++
 4 files changed, 60 insertions(+), 7 deletions(-)

Comments

Mark Brown Dec. 9, 2020, 8:28 p.m. UTC | #1 
On Sun, 6 Dec 2020 10:18:14 +0900, Damien Le Moal wrote:
> The Canaan Kendryte K210 RISC-V SoC includes a DesignWare apb_ssi V4
> SPI controller implemented with a maximum data frame size of 32-bits
> (SSI_MAX_XFER_SIZE=32 synthesis parameter).
> 
> This series of patches adds support for this SoC by implementing support
> for the 32-bits xfer size configuration. This is done in patch 2.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller
      commit: 7b14a272f9ac2438a85e59571fdb5a653d86430b
[2/3] spi: dw: Add support for 32-bits max xfer size
      commit: a51acc2400d47df0f87e1f011c63266421c594b9
[3/3] spi: dw: Add support for the Canaan K210 SoC SPI
      commit: b0dfd948379c79b8754e224e29b99d30ce0d79b8

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark