| Message ID | 20220805053019.996484-1-nagasuresh.relli@microchip.com |
|---|---|
| Headers | show |
| Series | Add support for Microchip QSPI controller | expand |
On Fri, Aug 05, 2022 at 08:50:37AM +0200, Krzysztof Kozlowski wrote: > On 05/08/2022 07:30, Naga Sureshkumar Relli wrote: > > Add the qspi driver to existing Polarfire SoC entry. > > > > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > This should be squashed with previous patch. It's perfectly fine to have a separate patch for MAINTAINERS like this.
On 05/08/2022 12:05, Mark Brown wrote: > On Fri, Aug 05, 2022 at 11:00:19AM +0530, Naga Sureshkumar Relli wrote: >> Add the qspi driver to existing Polarfire SoC entry. > >> +++ b/MAINTAINERS >> @@ -17146,6 +17146,7 @@ S: Supported >> F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> +F: drivers/spi/spi-microchip-core-qspi.c >> F: drivers/spi/spi-microchip-core.c >> F: include/soc/microchip/mpfs.h > > You should also add a pattern for the DT binding here. All of the bindings for the platform should have entries then right? I'll send a separate patch adding all of the missing bindings. I have a deferred change to the entry that needs to be sent to Arnd anyway so I can queue the two together. Nothing to be gained by waiting until this driver lands in 6.1+ to have MAINTAINERS coverage of the bindings :) Thanks, Conor.
This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI. changes in v3 ------------ 1. Added dev_err_probe() at places like probe failures 2. Split the dt-bindings one for adding coreqspi compatible and other one to add coreqspi as fallback to mpfs-qspi. changes in v2 ------------ 1. Replaced spi_alloc_master() with devm_spi_alloc_master() 2. Used dev_err_probe() when devm_spi_alloc_master() fails. 3. Added shared IRQ flag in the interrupt registration. 4. Updated the dt_bindings so that there is a differentiation between FPGA QSPI IP core and hard QSPI IP core. Naga Sureshkumar Relli (4): spi: dt-binding: document microchip coreQSPI spi: dt-binding: add coreqspi as a fallback for mpfs-qspi spi: microchip-core-qspi: Add support for microchip fpga qspi controllers MAINTAINERS: add qspi to Polarfire SoC entry .../bindings/spi/microchip,mpfs-spi.yaml | 15 +- MAINTAINERS | 1 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-microchip-core-qspi.c | 601 ++++++++++++++++++ 5 files changed, 623 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/spi-microchip-core-qspi.c