From patchwork Wed Nov 9 10:38:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4967 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CDA7623E0E for ; Wed, 9 Nov 2011 10:39:08 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id BF381A180CE for ; Wed, 9 Nov 2011 10:39:08 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id n26so2131830faa.11 for ; Wed, 09 Nov 2011 02:39:08 -0800 (PST) Received: by 10.152.112.10 with SMTP id im10mr1142783lab.2.1320835148487; Wed, 09 Nov 2011 02:39:08 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.10.72 with SMTP id g8cs163004lab; Wed, 9 Nov 2011 02:39:08 -0800 (PST) Received: by 10.213.34.65 with SMTP id k1mr158629ebd.101.1320835146673; Wed, 09 Nov 2011 02:39:06 -0800 (PST) Received: from eu1sys200aog112.obsmtp.com (eu1sys200aog112.obsmtp.com. [207.126.144.133]) by mx.google.com with SMTP id f46si1083660eea.77.2011.11.09.02.38.56 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Nov 2011 02:39:06 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.133 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.133; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.133 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob112.postini.com ([207.126.147.11]) with SMTP ID DSNKTrpYQBkXeGMeA1rKuzl5AyJh7MGJkYNb@postini.com; Wed, 09 Nov 2011 10:39:06 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 9E54190; Wed, 9 Nov 2011 10:38:55 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 5000F3F; Wed, 9 Nov 2011 10:38:09 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 4BC9CA807D; Wed, 9 Nov 2011 11:38:50 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 9 Nov 2011 11:38:54 +0100 From: Linus Walleij To: Grant Likely , Cc: , Viresh Kumar , Chris Blair , Linus Walleij Subject: [PATCH 1/6] spi/pl022: only enable RX interrupts when TX is complete Date: Wed, 9 Nov 2011 11:38:50 +0100 Message-ID: <1320835130-31201-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Chris Blair For interrupt mode transfers, start with only TX interrupts enabled to reduce the overall number of interrupts received. Once TX is complete, enable RX interrupts to complete the transfer. Signed-off-by: Chris Blair Signed-off-by: Linus Walleij --- drivers/spi/spi-pl022.c | 14 +++++++++----- 1 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 5559b22..b251926 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1244,9 +1244,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) if ((pl022->tx == pl022->tx_end) && (flag == 0)) { flag = 1; - /* Disable Transmit interrupt */ - writew(readw(SSP_IMSC(pl022->virtbase)) & - (~SSP_IMSC_MASK_TXIM), + /* Disable Transmit interrupt, enable receive interrupt */ + writew((readw(SSP_IMSC(pl022->virtbase)) & + ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } @@ -1379,12 +1379,16 @@ static void pump_transfers(unsigned long data) } err_config_dma: - writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); + /* enable all interrupts except RX */ + writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } static void do_interrupt_dma_transfer(struct pl022 *pl022) { - u32 irqflags = ENABLE_ALL_INTERRUPTS; + /* default is to enable all interrupts except RX - + * this will be enabled once TX is complete + */ + u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; /* Enable target chip */ pl022->cur_chip->cs_control(SSP_CHIP_SELECT);