From patchwork Tue Nov 22 08:24:18 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 5262 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6FF3A23FFD for ; Tue, 22 Nov 2011 08:25:14 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 386A8A18545 for ; Tue, 22 Nov 2011 08:25:14 +0000 (UTC) Received: by faaa26 with SMTP id a26so135351faa.11 for ; Tue, 22 Nov 2011 00:25:13 -0800 (PST) Received: by 10.152.104.1 with SMTP id ga1mr11004791lab.40.1321950313632; Tue, 22 Nov 2011 00:25:13 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs166939lal; Tue, 22 Nov 2011 00:25:13 -0800 (PST) Received: by 10.14.4.154 with SMTP id 26mr1241265eej.36.1321950310245; Tue, 22 Nov 2011 00:25:10 -0800 (PST) Received: from eu1sys200aog119.obsmtp.com (eu1sys200aog119.obsmtp.com. [207.126.144.147]) by mx.google.com with SMTP id e78si2985160eee.37.2011.11.22.00.24.56 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 00:25:10 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.147 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.147; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.147 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob119.postini.com ([207.126.147.11]) with SMTP ID DSNKTstcWGeQwu6rZidf3k9kK49fdhfl6MKR@postini.com; Tue, 22 Nov 2011 08:25:10 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 17D79DB; Tue, 22 Nov 2011 08:24:36 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 78B6C196F; Tue, 22 Nov 2011 08:24:36 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id B4AA7A8081; Tue, 22 Nov 2011 09:24:32 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 22 Nov 2011 09:24:35 +0100 From: Linus Walleij To: Grant Likely , Cc: , Viresh Kumar , Chris Blair , Linus Walleij Subject: [PATCH 1/7] spi/pl022: only enable RX interrupts when TX is complete Date: Tue, 22 Nov 2011 09:24:18 +0100 Message-ID: <1321950258-4683-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Chris Blair For interrupt mode transfers, start with only TX interrupts enabled to reduce the overall number of interrupts received. Once TX is complete, enable RX interrupts to complete the transfer. Reviewed-by: Viresh Kumar Signed-off-by: Chris Blair Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Fix comment style, add Viresh's Reviewed-by --- drivers/spi/spi-pl022.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 5559b22..5b7209f 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1244,9 +1244,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) if ((pl022->tx == pl022->tx_end) && (flag == 0)) { flag = 1; - /* Disable Transmit interrupt */ - writew(readw(SSP_IMSC(pl022->virtbase)) & - (~SSP_IMSC_MASK_TXIM), + /* Disable Transmit interrupt, enable receive interrupt */ + writew((readw(SSP_IMSC(pl022->virtbase)) & + ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } @@ -1379,12 +1379,17 @@ static void pump_transfers(unsigned long data) } err_config_dma: - writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); + /* enable all interrupts except RX */ + writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } static void do_interrupt_dma_transfer(struct pl022 *pl022) { - u32 irqflags = ENABLE_ALL_INTERRUPTS; + /* + * Default is to enable all interrupts except RX - + * this will be enabled once TX is complete + */ + u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; /* Enable target chip */ pl022->cur_chip->cs_control(SSP_CHIP_SELECT);