| Message ID | 20220221040717.3729-6-leilk.liu@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: mediatek: add single/quad mode support | expand |
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index 241c0f5880d3..6920ced5451e 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -55,12 +55,14 @@ properties: - description: clock used for the parent clock - description: clock used for the muxes clock - description: clock used for the clock gate + - description: clock used for the AHB bus, this clock is optional clock-names: items: - const: parent-clk - const: sel-clk - const: spi-clk + - const: spi-hclk mediatek,pad-select: $ref: /schemas/types.yaml#/definitions/uint32-array
this patch support spi-hclk. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> --- Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 2 ++ 1 file changed, 2 insertions(+)