From patchwork Sat Apr 9 12:08:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 559431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA52C433FE for ; Sat, 9 Apr 2022 12:09:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237195AbiDIMLi (ORCPT ); Sat, 9 Apr 2022 08:11:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241758AbiDIMLb (ORCPT ); Sat, 9 Apr 2022 08:11:31 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95257A6E24; Sat, 9 Apr 2022 05:09:22 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id s8so10615051pfk.12; Sat, 09 Apr 2022 05:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JIDrFKLNsEctZXQNacWwFCIZpHz5T6ma++EIZMHibGY=; b=kjeJ+8ybFuav/2E1QcfwEyLC0grQYYUgqfVUoP3TWNbdykcn3FuvG9QMgBsIjXnW/6 +sMEsppPzwiOKsUfnhp4HcyWgprlTgbdoHyoBT1lBJzebWTA7u0siWEoL1Yme21VwyEa JoOmVcoGCEqFiqFQJkVwUOql7PrW+iojilsyNXxQUu7+FnMPrB04nwIQmHs5EYI4JT2N wwqg8MLPhme/cA7JB4sQyjXcl9vzFW4MzSMvedGdZRxP75eSCqZNUi67rGsZJOC5GDbi Blg67UGpOZmTqi1ZR210szR2i4SEEmFWkSWdZb2p4iK+hEGDqNUZw48stu2l8pglVACo f6xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JIDrFKLNsEctZXQNacWwFCIZpHz5T6ma++EIZMHibGY=; b=fXxayfwmrffXAXP7cVHOUtv7Yog2x10l50Nl8fSM6ueTsEJ216gmaw4rdOkvPjEwTw NVKrcglLU3XexniYH61B0LP3l/NBB9ZBzlea4bX3ZaeAGdJNvH5BPbDNc/6rxmy2RI+Z PgaRtB1RFrcQJRAuBVLG5TM+Eqw0SZWMjD917veLWhGSqP6MblrUeqxSrdrQoy64Oo7C bdfRa4oVQdOcO6ZEcJp/o6cq2cxPI+dqSyYz6vfQjALpsn+CmSuuthOVJybY6dk09JK9 7oZqUezBXCVUXA3Inzd0hVZIygIIYnGWmt/kl4sERvTEmiQqcH2dPdhAFe7rRrC4sLUP OxSA== X-Gm-Message-State: AOAM530VtK/XOkCz14QgQ1vWsFN74wANJ0XgzKxyJlea0ND/ByzefmvU EGxaNB+zISJrs/H04MIBxRnPDX7I62KtC8RIE1R5ng== X-Google-Smtp-Source: ABdhPJzVLWfBVW0fiqRDnjbxiOd/l4AHyUuh6+F4EAJhezVBCLAqT493FkU3/oiaSTZAiwEfRAYvAQ== X-Received: by 2002:a63:a0d:0:b0:399:460c:ffb9 with SMTP id 13-20020a630a0d000000b00399460cffb9mr18983442pgk.43.1649506161890; Sat, 09 Apr 2022 05:09:21 -0700 (PDT) Received: from guoguo-omen.lan ([2401:c080:1400:4da2:b701:47d5:9291:4cf9]) by smtp.gmail.com with ESMTPSA id a85-20020a621a58000000b0050569a135besm8307357pfa.201.2022.04.09.05.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 05:09:21 -0700 (PDT) From: Chuanhong Guo To: linux-spi@vger.kernel.org Cc: Chuanhong Guo , Krzysztof Kozlowski , Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Roger Quadros , Thomas Bogendoerfer , Cai Huoqing , Florian Fainelli , Colin Ian King , Wolfram Sang , Paul Cercueil , Pratyush Yadav , Yu Kuai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list), linux-mtd@lists.infradead.org (open list:NAND FLASH SUBSYSTEM) Subject: [PATCH v5 4/5] spi: dt-bindings: add binding doc for spi-mtk-snfi Date: Sat, 9 Apr 2022 20:08:18 +0800 Message-Id: <20220409120819.3124209-5-gch981213@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220409120819.3124209-1-gch981213@gmail.com> References: <20220409120819.3124209-1-gch981213@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by: Chuanhong Guo Reviewed-by: Krzysztof Kozlowski --- Changes since v1: 1. add a blank line between properties in dt binding doc 2. rename ecc-engine to nand-ecc-engine for the generic properties Change since v2: none Change since v3: fix a missing rename in v1 Change since v4: fix typo: piplined -> pipelined .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml new file mode 100644 index 000000000000..6e6e02c91780 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI-NAND flash controller for MediaTek ARM SoCs + +maintainers: + - Chuanhong Guo + +description: | + The Mediatek SPI-NAND flash controller is an extended version of + the Mediatek NAND flash controller. It can perform standard SPI + instructions with one continuous write and one read for up-to 0xa0 + bytes. It also supports typical SPI-NAND page cache operations + in single, dual or quad IO mode with pipelined ECC encoding/decoding + using the accompanying ECC engine. There should be only one spi + slave device following generic spi bindings. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + + reg: + items: + - description: core registers + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + nand-ecc-engine: + description: device-tree node of the accompanying ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nand-ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; + }; + };