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Tue, 28 Jun 2022 13:44:33 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28~8r0TANA1p1424614246epcas2p1l; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220628044432epsmtrp2e1a72a51fe0de0497151a6a437be01e5~8r0S_iJrx2084220842epsmtrp23; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) X-AuditID: b6c32a45-471ff700000025c2-89-62ba87319e7d Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id A5.70.08905.0378AB26; Tue, 28 Jun 2022 13:44:32 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220628044432epsmtip1f70fcd8482e010ed119cdb03a9eef5af~8r0SvnclO2875028750epsmtip1d; Tue, 28 Jun 2022 04:44:32 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Date: Tue, 28 Jun 2022 13:42:20 +0900 Message-Id: <20220628044222.152794-3-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628044222.152794-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKJsWRmVeSWpSXmKPExsWy7bCmha5h+64kgw1zeSwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pm YKhraGlhrqSQl5ibaqvk4hOg65aZA3SdkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUg JafAvECvODG3uDQvXS8vtcTK0MDAyBSoMCE7Y8mzDpaCRToVj551szYwrlHuYuTkkBAwkWjY uouxi5GLQ0hgB6PE1ds7mSCcT4wSt06sYYNwvjFKXLuxiRmm5cL5p8wQib2MEu++LYZq+cgo Mf9eIyNIFZuArsSW56/ABosI3GSUmH62D6yKWeAGo8TeGeuBMhwcwgJhEpNfuII0sAioSqzo +skOYvMK2EscutIKtU5eYsP8XjCbU8BBYsHt7YwQNYISJ2c+YQGxmYFqmrfOBjtJQqCXQ2LO +f1QzS4Sffd6WCFsYYlXx7ewQ9hSEp/f7WWDsIslls76xATR3MAocXnbL6iEscSsZ+1ghzIL aEqs36UPYkoIKEscuQW1l0+i4/Bfdogwr0RHmxBEo7rEge3TWSBsWYnuOZ+hLvCQmHJ8Bwsk sCYzSvSvm8k8gVFhFpJ3ZiF5ZxbC4gWMzKsYxVILinPTU4uNCgzhcZycn7uJEZxetVx3ME5+ +0HvECMTB+MhRgkOZiUR3oVndiYJ8aYkVlalFuXHF5XmpBYfYjQFBvZEZinR5Hxggs8riTc0 sTQwMTMzNDcyNTBXEuf1StmQKCSQnliSmp2aWpBaBNPHxMEp1cBkyiZ83e/wNMVVE5x8zvVW m34y6FVVXnmy9a1bYYpya6v2/RnB4lPL5pXsqLb60b7xQbvYvalTTx+dG+b2cPJZt1udx9tX qfEX8e+puPvJ3md+6NTrSn7Zc501Tk3pNNW8sse799JJfsd/z7WmtC+yFPGQkY6/n+Czoc1o VemTh3VrLsz8Mj9vkWT0o1cyxq/cUwt3fl0b5Z68u3jLug7OBRf5GVkeccnInri3fIfGlp0s F+ep1h/xrrvzqWC3WJKjhI5Jqvk8WwsR33865UXrTgeY3y1m9/vBI5Y664q3mCDb94d+YkJe Jc7bGV70fGgumf/bf/2WBJfv2V+XLn00szk9PfXP+xcHHDcqzDqvxFKckWioxVxUnAgALoR2 7jgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSnK5B+64kgyvf1CwezNvGZrH4x3Mm i6kPn7BZXN6vbTH/yDlWi74XD5kt9r7eym6x6fE1VosZ5/cxWTR+vMlu0br3CLsDt8f1JZ+Y PTat6mTzuHNtD5vH5iX1Hn1bVjF6fN4kF8AWxWWTkpqTWZZapG+XwJWx5FkHS8EinYpHz7pZ GxjXKHcxcnJICJhIXDj/lLmLkYtDSGA3o8S671NZIRKyEs/e7WCHsIUl7rccYYUoes8osWvF C7AEm4CuxJbnrxhBEiICtxkl/jZuYwNxmAXuMEo8Wr6HCaRKWCBEYvXsCSwgNouAqsSKrp9g 3bwC9hKHrrQyQ6yQl9gwvxfM5hRwkFhwezsjiC0EVLN+51pWiHpBiZMzn4DNYQaqb946m3kC o8AsJKlZSFILGJlWMUqmFhTnpucWGxYY5qWW6xUn5haX5qXrJefnbmIER4KW5g7G7as+6B1i ZOJgPMQowcGsJMK78MzOJCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8F7pOxgsJpCeWpGanphak FsFkmTg4pRqYzneU+2evntRgX+N87Cxn1oJIvb2JewXf/Pra7jJV7sI/C+3VAb558rFHDdyW 7nwmEuYvYdK/gFdzunRcROcpC5fJwa9WL1DblTed8TJ70CKWY+79JQLrjP9++HguVHanrvaS 1SrrlE/6avnx+U5n9c/2eeKT8S/h8MzT4nOfbZoe4GE1z2tnoYjS8f9P+HM9XOvOvPvlEx5f uF01VUl5xm4xG5P3O/evnJjwkv170uJT7+8kRoWdbb0wfdqklIQz2227PlWdbS0vDn4dtmib kWFIr0Tt97M71tiq+23fs2dR6H5Hrzelj77tlnPjlHM54PmHW27ys4P3Z2YarNo0keet1zL+ a5unCpq6q1xYrMRSnJFoqMVcVJwIAHbzTMzzAgAA X-CMS-MailID: 20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28 References: <20220628044222.152794-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Modern exynos SoCs such as Exynos Auto v9 has different internal clock divider, for example "4". To support this internal value, this adds clk_div of the s3c64xx_spi_port_config and assign "2" as the default value to existing s3c64xx_spi_port_config. Signed-off-by: Chanho Park --- drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b3c50c7665fc..51a0e830441b 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. + * @clk_div: Internal clock divider, if not specified, use 2 as the default. * @quirks: Bitmask of known quirks * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. * @clk_from_cmu: True, if the controller does not include a clock mux and @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config { int rx_lvl_offset; int tx_st_done; int quirks; + int clk_div; bool high_speed; bool clk_from_cmu; bool clk_ioclk; @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) void __iomem *regs = sdd->regs; int ret; u32 val; + u32 div = sdd->port_conf->clk_div; /* Disable Clock */ if (!sdd->port_conf->clk_from_cmu) { @@ -668,16 +671,15 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); if (sdd->port_conf->clk_from_cmu) { - /* The src_clk clock is divided internally by 2 */ - ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); + ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); if (ret) return ret; - sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); val &= ~S3C64XX_SPI_PSR_MASK; - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) & S3C64XX_SPI_PSR_MASK); writel(val, regs + S3C64XX_SPI_CLK_CFG); @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_csinfo *cs = spi->controller_data; struct s3c64xx_spi_driver_data *sdd; int err; + u32 div = 2; sdd = spi_master_get_devdata(spi->master); if (spi->dev.of_node) { @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) pm_runtime_get_sync(&sdd->pdev->dev); + div = sdd->port_conf->clk_div; + /* Check if we can provide the requested rate */ if (!sdd->port_conf->clk_from_cmu) { u32 psr, speed; /* Max possible */ - speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); + speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); if (spi->max_speed_hz > speed) spi->max_speed_hz = speed; - psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; + psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; psr &= S3C64XX_SPI_PSR_MASK; if (psr == S3C64XX_SPI_PSR_MASK) psr--; - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz < speed) { if (psr+1 < S3C64XX_SPI_PSR_MASK) { psr++; @@ -914,7 +919,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } } - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); if (spi->max_speed_hz >= speed) { spi->max_speed_hz = speed; } else { @@ -1396,6 +1401,7 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { .fifo_lvl_mask = { 0x7f }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, .high_speed = true, }; @@ -1403,12 +1409,14 @@ static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7F }, .rx_lvl_offset = 13, .tx_st_done = 21, + .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, }; @@ -1416,6 +1424,7 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1425,6 +1434,7 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, @@ -1434,6 +1444,7 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = true, @@ -1444,6 +1455,7 @@ static struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset = 15, .tx_st_done = 25, + .clk_div = 2, .high_speed = true, .clk_from_cmu = true, .clk_ioclk = false,