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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:59 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/6] arm64: dts: exynos8895: Add serial_0/1 nodes Date: Sun, 20 Oct 2024 21:21:20 +0300 Message-ID: <20241020182121.377969-6-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index c95e4713a..c57b7243d 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -218,6 +218,19 @@ cmu_peric0: clock-controller@10400000 { "usi01", "usi02", "usi03"; }; + serial_0: serial@10430000 { + compatible = "samsung,exynos8895-uart"; + reg = <0x10430000 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; @@ -250,6 +263,19 @@ cmu_peric1: clock-controller@10800000 { "usi10", "usi11", "usi12", "usi13"; }; + serial_1: serial@10830000 { + compatible = "samsung,exynos8895-uart"; + reg = <0x10830000 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>;