From patchwork Mon May 5 16:41:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 888506 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CFAF26B094; Mon, 5 May 2025 16:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746463298; cv=none; b=f7U/UbSlXfFDfCJocEsCgV2y5DMpf2zKhU7ZpriH6YAsA8u48OpgSvmnn3O9+UXxMxMAfbEeasj6NHGa6d3gYtSywn0w8lySrznN8NQ2JoBU52p2B4o+ehEPy03lUcnd5+A2cDn4EgN/ZTNdhSoUAUh5pUcyTPdcMIgjTjy1TaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746463298; c=relaxed/simple; bh=9jkon8K3mFUIVCd/1uVumM/FKF0i2Zq69bPRbd7bkIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=COy50Vfq1+LF0ps71TFBDSunF5iGnGN2mUWOJ4dQnFDMq4T6Lq8dJpoQrx3i1YafZcbf0yFaLbXC9vh08Pk/Iodxcl3zDl3sRvpVp8y3E6FQYi+UkZdcCXAeOgZ5V5WFOq2J76Ptfl87JOjotloQRWjraVnOEQgNB3f41GWb30M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ngNac68J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ngNac68J" Received: by smtp.kernel.org (Postfix) with ESMTPS id AFFD1C4CEF3; Mon, 5 May 2025 16:41:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746463297; bh=9jkon8K3mFUIVCd/1uVumM/FKF0i2Zq69bPRbd7bkIo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ngNac68JOB0UIFtvVnmHSMjnY8OsQvu7KlF1yhQEgHtGwxhtpXpq3afK42GvBGihl jC/s4q6M7Wq2YP5xG73BnWTRkanpCZRb6jy67gJ1s3HcfuYCWrVfR7eJ5z32mx3u12 I/GDYWG42zg5Qzv/Za8kut4iFeM5U7jGKTd+xvovbkF3ylLYuw9VWehdW+DhmOgHYJ nO4de0NQIyGeSFDetA6eGJ/lD0gekFHPEwvUSA5tI4fKofhrF6KI8vS27pWXvWFcLV oGyHX32Zo6wePYsOR+RgQ/o+Vc6RrJq+LyM708DMuLcdd+dv94VHmyvIpuH8KY03RP KXmpdauAaLsHw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A31C2C3ABBE; Mon, 5 May 2025 16:41:37 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 05 May 2025 17:41:36 +0100 Subject: [PATCH v4 5/7] clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-dev-axi-clkgen-limits-v4-5-3ad5124e19e1@analog.com> References: <20250505-dev-axi-clkgen-limits-v4-0-3ad5124e19e1@analog.com> In-Reply-To: <20250505-dev-axi-clkgen-limits-v4-0-3ad5124e19e1@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746463295; l=3447; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=t0yUWo3oCD1jTmg3KYeSw2CHzqDGl83E2FrCAMjHYYY=; b=aJ5/yQTCmHQPkpI70a1EFrqj4aXv1J4dp2T0mp1CCzEFhUReVuSenddxACDbn7Rn+hbi404nF AY0MU858BkuBpF4xUDdoGUMP8t4Pu7g1+NE42E2mgOuF53iWEL+COrF X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá This patch adds support for setting the limits in struct axi_clkgen_limits in accordance with fpga speed grade, voltage, technology and family. This new information is extracted from two new registers implemented in the ip core that are only available for core versions higher or equal to 4. Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 60 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 31915f8f5565f2ef5d17c0b4a0c91a648005b3e6..a4cc6e1f0742fb22904c9a4c266198f62ede9c65 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -499,6 +499,54 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) return parent; } +static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen, + struct device *dev) +{ + unsigned int tech, family, speed_grade, reg_value; + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, ®_value); + tech = ADI_AXI_INFO_FPGA_TECH(reg_value); + family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); + speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); + + axi_clkgen->limits.fpfd_min = 10000; + axi_clkgen->limits.fvco_min = 600000; + + switch (speed_grade) { + case ADI_AXI_FPGA_SPEED_1 ... ADI_AXI_FPGA_SPEED_1LV: + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + break; + case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV: + axi_clkgen->limits.fvco_max = 1440000; + axi_clkgen->limits.fpfd_max = 500000; + if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) { + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_VOLTAGE, + ®_value); + if (ADI_AXI_INFO_FPGA_VOLTAGE(reg_value) < 950) { + axi_clkgen->limits.fvco_max = 1200000; + axi_clkgen->limits.fpfd_max = 450000; + } + } + break; + case ADI_AXI_FPGA_SPEED_3: + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fpfd_max = 550000; + break; + default: + return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n", + speed_grade); + }; + + /* Overwrite vco limits for ultrascale+ */ + if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) { + axi_clkgen->limits.fvco_max = 1600000; + axi_clkgen->limits.fvco_min = 800000; + } + + return 0; +} + static const struct clk_ops axi_clkgen_ops = { .recalc_rate = axi_clkgen_recalc_rate, .determine_rate = axi_clkgen_determine_rate, @@ -513,6 +561,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) { const struct axi_clkgen_limits *dflt_limits; struct axi_clkgen *axi_clkgen; + unsigned int pcore_version; struct clk_init_data init; const char *parent_names[2]; const char *clk_name; @@ -558,7 +607,16 @@ static int axi_clkgen_probe(struct platform_device *pdev) return -EINVAL; } - memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits)); + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_VERSION, &pcore_version); + + if (ADI_AXI_PCORE_VER_MAJOR(pcore_version) > 0x04) { + ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev); + if (ret) + return ret; + } else { + memcpy(&axi_clkgen->limits, dflt_limits, + sizeof(axi_clkgen->limits)); + } clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names",