@@ -30,6 +30,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
@@ -74,6 +74,19 @@ ref24: ref24M {
clock-frequency = <24000000>;
};
+ ref25: clock-25000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ pllb: clock@204 {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x204>;
+ };
+
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
@@ -105,6 +118,15 @@ clkuart3: uart3 {
enable-reg = <0x250>;
enable-bit = <4>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -114,6 +136,18 @@ timer@d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller@d8002000 {
+ compatible = "via,vt8500-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
@@ -30,6 +30,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
@@ -203,6 +203,15 @@ clksdhc: sdhc {
enable-reg = <0x254>;
enable-bit = <18>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -212,6 +221,18 @@ timer@d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller@d8002000 {
+ compatible = "wm,wm8505-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb@d8007100 {
compatible = "via,vt8500-ehci";
reg = <0xd8007100 0x200>;
@@ -31,6 +31,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
@@ -175,6 +175,15 @@ clksdhc: sdhc {
enable-reg = <0x254>;
enable-bit = <18>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -184,6 +193,18 @@ timer@d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller@d8002000 {
+ compatible = "wm,wm8650-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
@@ -24,6 +24,43 @@ i2c: i2c {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
@@ -240,6 +240,15 @@ clki2c1: i2c1clk {
enable-reg = <0x250>;
enable-bit = <9>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -256,6 +265,18 @@ timer@d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller@d8002000 {
+ compatible = "wm,wm8750-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
@@ -42,6 +42,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
@@ -217,6 +217,15 @@ clksdhc: sdhc {
enable-reg = <0x250>;
enable-bit = <0>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -243,6 +252,18 @@ timer@d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller@d8002000 {
+ compatible = "wm,wm8850-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
@@ -16,6 +16,43 @@ memory@0 {
};
};
+&sflash {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition@2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition@3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
The serial flash controller resides at the same MMIO address in all known VIA/WonderMedia SoCs, and its clock uses the same enable bit and divisor reg on all SoCs, feeding off PLL B. Add respective DT nodes using SoC specific compatibles for the controller to make it future proof in case any differences in behavior are discovered later on. All known boards boot from SPI NOR flash, so their flash chips are at CS0 and mapped by the boot ROM at the end of their CPU address space. Add respective DT nodes in board-specific dts files too. Signed-off-by: Alexey Charkov <alchark@gmail.com> --- arch/arm/boot/dts/vt8500/vt8500-bv07.dts | 37 ++++++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/vt8500.dtsi | 34 +++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/wm8505-ref.dts | 37 ++++++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/wm8505.dtsi | 21 ++++++++++++++++ arch/arm/boot/dts/vt8500/wm8650-mid.dts | 37 ++++++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/wm8650.dtsi | 21 ++++++++++++++++ arch/arm/boot/dts/vt8500/wm8750-apc8750.dts | 37 ++++++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/wm8750.dtsi | 21 ++++++++++++++++ arch/arm/boot/dts/vt8500/wm8850-w70v2.dts | 37 ++++++++++++++++++++++++++++ arch/arm/boot/dts/vt8500/wm8850.dtsi | 21 ++++++++++++++++ arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts | 37 ++++++++++++++++++++++++++++ 11 files changed, 340 insertions(+)