From patchwork Mon May 12 14:46:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= X-Patchwork-Id: 889610 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C95C22A4D8; Mon, 12 May 2025 14:46:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747061207; cv=none; b=hhIT5eA6QrXK2RgyB1oH0ZnBTYDDEqS74k8kU3kBVvqOwfv4iYEnCP7BtGSypLXhGjTOBepzTwXuV6s3eVEWD7rbnwVUg/hrKeIw6bkDqo4N6TPY3MugUzgXWL8bxRNTOZKLqigG6wu4vwG73i+AcbDF2220xAnvDTpH5NUa4vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747061207; c=relaxed/simple; bh=HI59+3VsZAHzDG2lW8mj78HPsyNMQFBt0V6LHST9s0s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tuDrNF21vurpkh3Y4x0Ph/nycMf1jyEDkk6fdxzXdbRVGyP4gVzaLI+8mJEFpkcjq1GV/iIidZmwXCUGt/IxmrtXHR1yq7zI+ch7b8x8PQPYSBR3wScgsFe1Y7LtzLXaTo77sYuSmvkTm7ms6LRJZTkEZ9C92H4M7t5QK1RllxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZRX4MrHf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZRX4MrHf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 999D4C4CEF2; Mon, 12 May 2025 14:46:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747061206; bh=HI59+3VsZAHzDG2lW8mj78HPsyNMQFBt0V6LHST9s0s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZRX4MrHfcdd624JDKblY4ihWOx4yVyE8kZvLksV1vteQiP5jI18efVUOx27RhG+JC pNyGc5kGEGqpfWNeWwVr3a+/XeiadPpuv7K2e7SeHYNS4Rwtk8+WcX6LxhLZQYC0Tq XwgYsPNNVjtHyyqc/CgRRyv8oL8kcOa14b/y2/RgKl9VrDtmM5r3adyInx3eSo1/Dc scHVJBFNjDTE86C6+cbC4grtlLAog3WpJYirbTB6eO+7JMWpETfWJhRT4useO1Jpw0 6guKnqswpFld/pRrUJa/5wKQ1wKAmbRO8D7NGmLweiR1QOydYf8Vh2iIpUtDfRhgl0 ksbQuNMmZja8g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 884E8C3ABD8; Mon, 12 May 2025 14:46:46 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Mon, 12 May 2025 15:46:44 +0100 Subject: [PATCH v5 1/7] clk: clk-axi-clkgen: fix fpfd_max frequency for zynq Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-dev-axi-clkgen-limits-v5-1-a86b9a368e05@analog.com> References: <20250512-dev-axi-clkgen-limits-v5-0-a86b9a368e05@analog.com> In-Reply-To: <20250512-dev-axi-clkgen-limits-v5-0-a86b9a368e05@analog.com> To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org, dmaengine@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org Cc: Stephen Boyd , Michael Turquette , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Vinod Koul , Jean Delvare , Guenter Roeck , Michael Hennerich , Jonathan Cameron , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , David Lechner , Mark Brown , Mike Turquette X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747061206; l=999; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=5+y858CS+pLM6RSN4Bbzxos5w9xYK0rwoYDgzKAlxLk=; b=OVRuv3PQZMJbAdpkX3/v33TFz5h3pR0mpJ/HlJHAFPI6R1qT5lYXbV3V+gx2XmIM+G1uZyxD4 eWsjHmQWwogC6U8qF8ShTYDKulU4473tL65FYVZH2zXiY57IEyaoMRi X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno Sá The fpfd_max frequency should be set to 450 MHz instead of 300 MHz. Well, it actually depends on the platform speed grade but we are being conservative for ultrascale so let's be consistent. In a following change we will set these limits at runtime. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sá --- drivers/clk/clk-axi-clkgen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 934e53a96dddac8ed61dd109cfc188f3a2a0539a..00bf799964c61a3efc042b0f3a9ec3bc8625c9da 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -118,7 +118,7 @@ static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = { static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { .fpfd_min = 10000, - .fpfd_max = 300000, + .fpfd_max = 450000, .fvco_min = 600000, .fvco_max = 1200000, };