From patchwork Wed Feb 3 06:31:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 375766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FDBDC433DB for ; Wed, 3 Feb 2021 06:35:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABEBD64DD9 for ; Wed, 3 Feb 2021 06:35:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbhBCGeh (ORCPT ); Wed, 3 Feb 2021 01:34:37 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:24576 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231542AbhBCGef (ORCPT ); Wed, 3 Feb 2021 01:34:35 -0500 X-UUID: 75167f3385c64e8e9769cb95877eae5a-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KRCVDtSrRgehzxm0fduIGauOJq45reVWKzALRHgkuIU=; b=WpygqJlCN+cbscJ5VwiFUFtgFv9HeH7DkhifvUsp7//ppKiBF7qGg3qv3PFYiBLi/gdbCxTZdD9d7Y8Lr3G4YvkRQYdMPSuDhaBoVflxZmDT8nRgLZRw5iximm551X/rBbBnWKtWoSeZYzmmGPUfBH0jiKyULsw/akySl+oV8i0=; X-UUID: 75167f3385c64e8e9769cb95877eae5a-20210203 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2082715301; Wed, 03 Feb 2021 14:32:52 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 14:32:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 14:32:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH 3/3] arm64: dts: mt8195: add USB related nodes Date: Wed, 3 Feb 2021 14:31:59 +0800 Message-ID: <20210203063159.11021-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210203063159.11021-1-chunfeng.yun@mediatek.com> References: <20210203063159.11021-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: B788B26AA748834F35E1F108DA8F78F6660A6C51C78035BFD44E6544A033CAD72000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add USB nodes, PHY nodes and some fixed regulator nodes. We prefer to use mt8192's compatible for the first USB controller (port0), there is no wrong with the SOF/ITP interval; but for other controllers (port1~port3) should use mt8195's one due to the wrong default setting of SOF/ITP interval which should be calculated from 48M, but not 24M by default. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 70 +++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 163 ++++++++++++++++++++ 2 files changed, 233 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 7264232bb7e9..a60682752e19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mt8195.dtsi" #include "mt6359.dtsi" +#include / { model = "MediaTek MT8195 evaluation board"; @@ -49,6 +50,36 @@ enable-active-high; regulator-always-on; }; + + usb_p0_vbus: regulator@2 { + compatible = "regulator-fixed"; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p2_vbus: regulator@3 { + compatible = "regulator-fixed"; + gpio = <&pio 131 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p3_vbus: regulator@4 { + compatible = "regulator-fixed"; + gpio = <&pio 5 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; }; &pmic { @@ -156,6 +187,22 @@ status = "okay"; }; +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status="okay"; +}; + +&u3phy3 { + status="okay"; +}; + &pio { nor_pins_default: nordefault { pins0 { @@ -311,3 +358,26 @@ }; }; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p0_vbus>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p3_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ccb9d24b1c1e..60c75b23cf03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -914,6 +915,83 @@ status = "disabled"; }; + xhci0: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>, + <&topckgen CLK_TOP_SSUSB_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P1_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P2_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P3_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + pcie0: pcie@112f0000 { device_type = "pci"; compatible = "mediatek,mt8195-pcie"; @@ -998,6 +1076,40 @@ status = "disabled"; }; + u3phy2: usb-phy2@11c40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb2-phy2@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy3: usb-phy3@11c50000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb2-phy3@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + i2c5: i2c5@11d00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -1138,6 +1250,57 @@ #clock-cells = <1>; }; + u3phy1: usb-phy1@11e30000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0x1000>; + status = "disabled"; + + u2port1: usb2-phy1@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb3-phy1@700 { + reg = <0x700 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy0: usb-phy0@11e40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0x1000>; + status = "disabled"; + + u2port0: usb2-phy0@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb3-phy0@700 { + reg = <0x700 0 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + pciephy: phy@11e80000 { compatible = "mediatek,mt8195-pcie-phy"; #address-cells = <2>;