diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt
deleted file mode 100644
index 4aa368447b1e..000000000000
--- a/Documentation/devicetree/bindings/usb/dwc3-st.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-ST DWC3 glue logic
-
-This file documents the parameters for the dwc3-st driver.
-This driver controls the glue logic used to configure the dwc3 core on
-STiH407 based platforms.
-
-Required properties:
- - compatible	: must be "st,stih407-dwc3"
- - reg		: glue logic base address and USB syscfg ctrl register offset
- - reg-names	: should be "reg-glue" and "syscfg-reg"
- - st,syscon	: should be phandle to system configuration node which
-		  encompasses the glue registers
- - resets	: list of phandle and reset specifier pairs. There should be two entries, one
-		  for the powerdown and softreset lines of the usb3 IP
- - reset-names	: list of reset signal names. Names should be "powerdown" and "softreset"
-See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
-See: Documentation/devicetree/bindings/reset/reset.txt
-
- - #address-cells, #size-cells : should be '1' if the device has sub-nodes
-   with 'reg' property
-
- - pinctl-names	: A pinctrl state named "default" must be defined
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-
- - pinctrl-0	: Pin control group
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-
- - ranges	: allows valid 1:1 translation between child's address space and
-		  parent's address space
-
-Sub-nodes:
-The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
-example below. The DT binding details of dwc3 can be found in:
-Documentation/devicetree/bindings/usb/snps,dwc3.yaml
-
-NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
-is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
-or "device".
-
-[1] Documentation/devicetree/bindings/usb/usb-drd.yaml
-
-Example:
-
-st_dwc3: dwc3@8f94000 {
-	compatible	= "st,stih407-dwc3";
-	reg		= <0x08f94000 0x1000>, <0x110 0x4>;
-	reg-names	= "reg-glue", "syscfg-reg";
-	st,syscfg	= <&syscfg_core>;
-	resets		= <&powerdown STIH407_USB3_POWERDOWN>,
-			  <&softreset STIH407_MIPHY2_SOFTRESET>;
-	reset-names	= "powerdown", "softreset";
-	#address-cells	= <1>;
-	#size-cells	= <1>;
-	pinctrl-names	= "default";
-	pinctrl-0	= <&pinctrl_usb3>;
-	ranges;
-
-	dwc3: dwc3@9900000 {
-		compatible	= "snps,dwc3";
-		reg		= <0x09900000 0x100000>;
-		interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;
-		dr_mode		= "host";
-		phy-names	= "usb2-phy", "usb3-phy";
-		phys		= <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/usb/st,stih407-dwc3.yaml b/Documentation/devicetree/bindings/usb/st,stih407-dwc3.yaml
new file mode 100644
index 000000000000..709cdb17f28d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st,stih407-dwc3.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/st,stih407-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST DWC3 glue logic
+
+description:
+  This binding describes the parameters for the dwc3-st driver,
+  which controls the glue logic used to configure the DWC3 core on
+  STiH407-based platforms.
+
+maintainers:
+  - Mauro Carvalho Chehab <mchehab@kernel.org>
+
+properties:
+  compatible:
+    const: st,stih407-dwc3
+
+  reg:
+    # minItems: 2
+    items:
+      - description: Glue logic base address.
+      - description: USB syscfg ctrl register offset.
+
+  reg-names:
+    # minItems: 2
+    items:
+      - const: reg-glue
+      - const: syscfg-reg
+
+  st,syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Phandle to system configuration node which.
+
+  resets:
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: powerdown
+      - const: softreset
+
+  st,syscfg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  pinctrl-names:
+    items:
+      - const: default
+
+  pinctrl-0:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+      Pin control group
+      See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+  ranges:
+    description: Valid 1:1 translation between child's and parent's address space.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+  - pinctrl-names
+  - pinctrl-0
+  - ranges
+
+additionalProperties: false
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    type: object
+    description: DWC3 core sub-node
+    $ref: snps,dwc3.yaml#
+    unevaluatedProperties: false
+    properties:
+      dr_mode:
+        enum:
+          - host
+          - device
+        description: |
+          Specifies the operating mode. The default value "otg" is not
+          supported by this SoC. Valid values are "host" or "device".
+          See: Documentation/devicetree/bindings/usb/usb-drd.yaml
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/reset/stih407-resets.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    st_dwc3: dwc3@8f94000 {
+        compatible	= "st,stih407-dwc3";
+        reg		= <0x08f94000 0x1000>, <0x110 0x4>;
+        reg-names	= "reg-glue", "syscfg-reg";
+        st,syscfg	= <&syscfg_core>;
+        resets		= <&powerdown STIH407_USB3_POWERDOWN>,
+              <&softreset STIH407_MIPHY2_SOFTRESET>;
+        reset-names	= "powerdown", "softreset";
+        #address-cells	= <1>;
+        #size-cells	= <1>;
+        pinctrl-names	= "default";
+        pinctrl-0	= <&pinctrl_usb3>;
+        ranges;
+
+        dwc3: usb@9900000 {
+            compatible	= "snps,dwc3";
+            reg		= <0x09900000 0x100000>;
+            interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;
+            dr_mode		= "host";
+            phy-names	= "usb2-phy", "usb3-phy";
+            phys		= <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
+        };
+    };
