From patchwork Tue Mar 1 05:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 548708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E486C4332F for ; Tue, 1 Mar 2022 05:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbiCAFo7 (ORCPT ); Tue, 1 Mar 2022 00:44:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232159AbiCAFo6 (ORCPT ); Tue, 1 Mar 2022 00:44:58 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3E4F56748; Mon, 28 Feb 2022 21:44:16 -0800 (PST) X-UUID: 0315ce44ac0349e49da60f0731628d1f-20220301 X-UUID: 0315ce44ac0349e49da60f0731628d1f-20220301 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1762921973; Tue, 01 Mar 2022 13:44:08 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 1 Mar 2022 13:44:07 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Mar 2022 13:44:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 1 Mar 2022 13:44:06 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , Rex-BC Chen Subject: [RESEND V2 0/3] Add watchdog support for MT8186 SoC Date: Tue, 1 Mar 2022 13:44:02 +0800 Message-ID: <20220301054405.25021-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org resend v2: 1. Fix topic to V2. v2: 1. Squash [1] into [2] in v1. 2. Add tags of acked-by and reviewed-by. [1]: [3/4] dt-bindings: reset: mt8186: add DSI reset bit for MMSYS [2]: [2/4] dt-bindings: reset: mt8186: add toprgu reset-controller header file v1: 1. Add mt8186-resets.h to define definition of reset bits. 2. Add wdt compatible for MT8186. Rex-BC Chen (1): dt-bindings: watchdog: Add compatible for MediaTek MT8186 Runyang Chen (2): dt-bindings: reset: mt8186: add reset-controller header file watchdog: mediatek: mt8186: add wdt support .../devicetree/bindings/watchdog/mtk-wdt.txt | 1 + drivers/watchdog/mtk_wdt.c | 6 ++++ include/dt-bindings/reset/mt8186-resets.h | 36 +++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 include/dt-bindings/reset/mt8186-resets.h