| Message ID | 1485540470-11469-1-git-send-email-will.deacon@arm.com |
|---|---|
| Headers | show |
| Series | Add support for the ARMv8.2 Statistical Profiling Extension | expand |
On 27/01/17 18:07, Will Deacon wrote: > The SPE architecture requires each exception level to enable access > to the SPE controls for the exception level below it, since additional > context-switch logic may be required to handle the buffer safely. > > This patch allows EL1 (host) access to the SPE controls when entered at > EL2. > > Cc: Marc Zyngier <marc.zyngier@arm.com> > Signed-off-by: Will Deacon <will.deacon@arm.com> Definitely more readable than the initial version! ;-) Acked-by: Marc Zyngier <marc.zyngier@arm.com> M. -- Jazz is not dead. It just smells funny...
On Fri, Jan 27, 2017 at 06:07:43PM +0000, Will Deacon wrote: > The SPE architecture requires each exception level to enable access > to the SPE controls for the exception level below it, since additional > context-switch logic may be required to handle the buffer safely. > > This patch allows EL1 (host) access to the SPE controls when entered at > EL2. > > Cc: Marc Zyngier <marc.zyngier@arm.com> > Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/kernel/head.S | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index 4b1abac3485a..7f625d2e8e45 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -592,15 +592,26 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems > #endif > > /* EL2 debug */ > - mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer > - sbfx x0, x0, #8, #4 > + mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer > + sbfx x0, x1, #8, #4 > cmp x0, #1 > b.lt 4f // Skip if no PMU present > mrs x0, pmcr_el0 // Disable debug access traps > ubfx x0, x0, #11, #5 // to EL2 and allow access to > 4: > - csel x0, xzr, x0, lt // all PMU counters from EL1 > - msr mdcr_el2, x0 // (if they exist) > + csel x3, xzr, x0, lt // all PMU counters from EL1 > + > + /* Statistical profiling */ > + ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer > + cbz x0, 6f // Skip if SPE not present > + cbnz x2, 5f // VHE? > + mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) > + orr x3, x3, x1 // If we don't have VHE, then > + b 6f // use EL1&0 translation. > +5: // For VHE, use EL2 translation > + orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 > +6: > + msr mdcr_el2, x3 // Configure debug traps > > /* Stage-2 translation */ > msr vttbr_el2, xzr > -- > 2.1.4 >
Hi all, This is the third posting of the patches previously posted here: rfcv1: http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/476450.html rfcv2: http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/479387.html Changes since RFCv2 include: * Change compatible string * Renamed PMU * Simplified EL2 init code * Dropped the RFC tag * Added acks There's also now an official ARM blog giving a high-level overview of what SPE is: https://community.arm.com/processors/b/blog/posts/statistical-profiling-extension-for-armv8-a All comments welcome, Will --->8 Will Deacon (10): arm64: cpufeature: allow for version discrepancy in PMU implementations arm64: cpufeature: Don't enforce system-wide SPE capability arm64: KVM: Save/restore the host SPE state when entering/leaving a VM arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 genirq: export irq_get_percpu_devid_partition to modules perf/core: Export AUX buffer helpers to modules perf: Directly pass PERF_AUX_* flags to perf_aux_output_end perf/core: Add PERF_AUX_FLAG_COLLISION to report colliding samples drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension dt-bindings: Document devicetree binding for ARM SPE Documentation/devicetree/bindings/arm/spe-pmu.txt | 20 + arch/arm64/include/asm/kvm_arm.h | 3 + arch/arm64/include/asm/kvm_host.h | 7 +- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kernel/cpufeature.c | 9 +- arch/arm64/kernel/head.S | 19 +- arch/arm64/kvm/debug.c | 6 + arch/arm64/kvm/hyp/debug-sr.c | 66 +- arch/arm64/kvm/hyp/switch.c | 17 +- arch/x86/events/intel/bts.c | 11 +- arch/x86/events/intel/pt.c | 11 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 5 +- drivers/perf/Kconfig | 8 + drivers/perf/Makefile | 1 + drivers/perf/arm_spe_pmu.c | 1245 +++++++++++++++++++++ include/linux/perf_event.h | 4 +- include/uapi/linux/perf_event.h | 1 + kernel/events/ring_buffer.c | 16 +- kernel/irq/irqdesc.c | 1 + 19 files changed, 1421 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spe-pmu.txt create mode 100644 drivers/perf/arm_spe_pmu.c -- 2.1.4